Method of making contact alignment for nonvolatile memory devices

Claim 1

A nonvolatile memory array, comprising: a semiconductor substrate; an array of rectangular field oxide regions in said substrate; a plurality of parallel control gates on said substrate in a first direction, said control gates grouped in pairs with both control gates of a pair passing over opposite ends of each field oxide region lying in a column in the first direction, wherein between the two control gates of every pair are a plurality of active regions separated by the field oxide regions, and wherein between each pair of control gates is a continuous active region within said substrate, and further wherein each control gate has a top and sides covered by a single, continuous layer of oxide; a plurality of polycrystalline silicon ground lines, one between each pair of control gates and in continuous contact with the continuous active region therebetween, wherein each polycrystalline silicon ground line is separated from the adjacent control gates by the oxide layer and fills a space between the adjacent control gates, and wherein the ground lines extend partway over the top of the adjacent control gates and are separated therefrom by the oxide layer; and a plurality of bit lines crossing said control gates and said polycrystalline silicon ground lines in a second direction orthogonal to the first direction, said bit lines contacting the active regions between the paired control gates.