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US5446850A Expired / Lapsed US ⏱️ 0.0 years remaining

Cross-cache-line compounding algorithm for scism processors

Assignee: International Business Machines Corp
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Filing: 1994-07-27
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Granted: 1995-08-29
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Expires: 2014-07-27
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Abstract

Abstract A system for compounding instructions across cache line boundaries transfers an instruction line from a relatively slow memory to a instruction compounding unit if there is a miss for an instruction in that line in the instruction cache. At the same time the numerically preceding instruction in cache is transferred to the instruction compounding unit and instructions from the two lines are compounded. If a numerically preceding cache line has been compounded with a cache line that has been deleted and then replaced, compounding tags for the numerically preceding cache line are deleted.

Inventors

  • 👤 Thomas L. Jeremiah
  • 👤 Bartholomew Blaner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 22:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3802; G06F9/3808; G06F9/3812; G06F9/3816; G06F9/3836; G06F9/3842; G06F9/3853

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 324 words
A data processing system in which instructions are transferred in blocks called instruction lines from a relatively low speed memory to a relatively high speed cache memory and from which cache memory instruction lines are fetched for execution and are deleted a line at a time, said system including an instruction compounding unit in which instructions are processed in order to generate tag information that indicates instructions that can be executed in parallel, said data processing system comprising in combination: means to address a first instruction line in said cache memory in order to transfer said first instruction line from said cache memory to an instruction fetch unit; means to generate a miss signal if said first instruction line is not resident in said high speed cache memory; means responsive to said miss signal for transferring said first instruction line from said relatively low speed memory to said instruction compounding unit; means responsive to said miss signal for determining an address of a second instruction line that is next in succession to said first instruction line for transfer to said instruction fetch unit; means for transferring said second instruction line to said instruction compounding unit if said second instruction line resides in said cache memory; said instruction compounding unit processing instructions from said first instruction line and said second instruction line in order to generate tag information indicating an instruction in said first instruction line that can be executed in parallel with an instruction in said second instruction line means for determining if an instruction line in said cache memory has been deleted and replaced prior to its execution; means to determine if said deleted and replaced instruction line contains instructions that have been compounded with another instruction line in said cache memory; and means to delete tag information that indicates an instruction in said another instruction line can be compounded with an instruction in said instruction line that has been deleted and replaced.
Claim 2
Dependent Claim 324 words
A data processing system in which instructions are transferred in blocks called instruction lines from a relatively low speed memory to a relatively high speed cache memory and from which cache memory instruction lines are fetched for execution and are deleted a line at a time, said system including an instruction compounding unit in which instructions are processed in order to generate tag information that indicates instructions that can be executed in parallel, said data processing system comprising in combination: means to address a first instruction line in said cache memory in order to transfer said first instruction line from said cache memory to an instruction fetch unit; means to generate a miss signal if said first instruction line is not resident in said high speed cache memory; means responsive to said miss signal for transferring said first instruction line from said relatively low speed memory to said instruction compounding unit; means responsive to said miss signal for determining an address of a second instruction line that is next in succession to said first instruction line for transfer to said instruction fetch unit; means for transferring said second instruction line to said instruction compounding unit if said second instruction line resides in said cache memory; said instruction compounding unit processing instructions from said first instruction line and said second instruction line in order to generate tag information indicating an instruction in said first instruction line that can be executed in parallel with an instruction in said second instruction line means for determining if an instruction line in said cache memory has been deleted and replaced prior to its execution; means to determine if said deleted and replaced instruction line contains instructions that have been compounded with another instruction line in said cache memory; and means to delete tag information that indicates an instruction in said another instruction line can be compounded with an instruction in said instruction line that has been deleted and replaced.
Claim 3
Dependent Claim 41 words
A data processing system as in claim 1 wherein said second instruction line is transferred to said instruction compounding unit during an interval when said first instruction line is transferred from said relatively low speed memory to said instruction compounding unit.
Claim 4
Dependent Claim 24 words
A processing system as in claim 1, wherein said means for determining an address includes means to decrement the address of a missed instruction.
Claim 5
Dependent Claim 24 words
A processing system as in claim 1, wherein said means for determining an address includes means to decrement the address of a missed instruction.
Claim 6
Dependent Claim 24 words
A processing system as in claim 1, wherein said means for determining an address includes means to decrement the address of a missed instruction.

References Cited (Backward Citations)

US5214763A Cited
US5197135A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-08-28 1999-02-27 1999-08-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-08-28 2003-02-27 2003-08-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-08-28 2007-02-27 2007-08-29 $7700.00 Window Closed / Lapsed

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