US5446746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Path memory apparatus of a viterbi decoder
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-08-27
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Granted: 1995-08-29
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Expires: 2013-08-27
Abstract
Abstract The path memory apparatus of a Viterbi decoder having an add-compare-select circuit for producing path select signals and a minimum state number every symbol period comprises a first selector for selecting between the path select signals and feedback signals in accordance with a start clock; a memory for receiving the output of a first selector and shifting the received output thereof in one direction in accordance with a system clock, and applying the output as the feedback signal; a second selector for selecting one among the outputs of the memory in accordance with a current state number; a third selector for selecting between the minimum state number and a next state number in accordance with the start clock, to produce the current state number; a trace-back calculator for receiving the current state number and the output of second selector and then producing the next state number; and a data convertor for performing an operating on the next state numbers, to produce a decoded information symbol per each symbol period.
Inventors
- 👤 Il-keun Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:19
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/65; H03M13/6502; H03M13/37; H03M13/39; H03M13/3961; H03M13/41; H03M13/4161; H03M13/4169
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
A path memory apparatus of a Viterbi decoder having an add-compare-select means for producing path select signals and a minimum state number every symbol period, the path memory apparatus comprising: first selecting means for selecting between the path select signals and feedback signals in accordance with a start clock; storing means for receiving the outputs of said first selecting means and shifting the received output in one direction in accordance with a system clock, and applying the outputs thereof to said first selecting means as the feedback signals; second selecting means for selecting one among the outputs of the memory means in accordance with a current state number; third selecting means for selecting between the minimum state number and a next state number in accordance with the start clock to produce the current state number; trace-back calculating means for receiving the current state number and the output of said second selecting means and then producing the next state number; and data converting means for operating on the next state numbers to produce a decoded information symbol per each symbol period.
Claim 2
Dependent Claim
180 words
A path memory apparatus of a Viterbi decoder having an add-compare-select means for producing path select signals and a minimum state number every symbol period, the path memory apparatus comprising: first selecting means for selecting between the path select signals and feedback signals in accordance with a start clock; storing means for receiving the outputs of said first selecting means and shifting the received output in one direction in accordance with a system clock, and applying the outputs thereof to said first selecting means as the feedback signals; second selecting means for selecting one among the outputs of the memory means in accordance with a current state number; third selecting means for selecting between the minimum state number and a next state number in accordance with the start clock to produce the current state number; trace-back calculating means for receiving the current state number and the output of said second selecting means and then producing the next state number; and data converting means for operating on the next state numbers to produce a decoded information symbol per each symbol period.
Claim 3
Dependent Claim
30 words
A path memory apparatus claimed in claim 1, wherein said memory means comprises a plurality of shift registers each having tb+1 stages, tb being a value representing the trace-back depth.
Claim 4
Dependent Claim
18 words
A path memory apparatus claimed in claim 1, wherein said first selecting means comprises a plurality of multiplexers.
Claim 5
Dependent Claim
18 words
A path memory apparatus claimed in claim 1, wherein said third selecting means comprises a plurality of multiplexers.
Claim 6
Dependent Claim
20 words
A path memory apparatus claimed in claim 1, wherein said data converting means is implemented by a combinational logic circuit.
Claim 7
Dependent Claim
19 words
A path memory apparatus claimed in claim 1, wherein said start clock is synchronously active every symbol clock pulse.
Claim 8
Dependent Claim
29 words
A path memory apparatus claimed in claim 1, wherein said system clock is active tb times within one symbol duration, where tb is a value representing the trace-back depth.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |