Fast memory power-on diagnostics using DMA

Claim 2

In a processing system including a processor unit coupled to a memory means for executing instructions stored in the memory means that access and utilize data stored in and retrieved from the memory means during access cycles, a testing system for interactively testing the memory means while the processor is executing stored instructions comprising: interrupting means for controlling access to the memory means by the testing system while excluding access to the memory means by the processor unit during an access cycle; addressing means for supplying address signals to the memory means to select successive location in the memory means not utilized by the processor unit; writing means for storing test data in the memory means at locations addressed by the addressing means; reading means for retrieving data from the memory means at locations addressed by the addressing means; and comparing means coupled to receive test data from the writing means and data retrieved from the memory means by the reading means for verifying that the data stored in locations by the writing means is equal to the data retrieved from the same locations by the reading means.

Claim 3

The testing system claimed in claim 1 wherein the comparing means includes signalling means for supplying an error signal to the processor unit when an unequal comparison by the comparing means.

Claim 4

The testing system claimed in claim 2 including means for coupling the error signal to the processor unit; means for coupling the address signals to the processor unit; and means in said processor unit responsive to the error signal and to the address signals for indicating the location in the memory means at which an error occurred.

Claim 5

A memory test unit comprising: memory means for storing data and having address means for accessing an addressed location and data means for selectively reading and writing data at an accessed location; processor means for executing predetermined operations and including addressing means for supplying addresses, data input means for accepting data, and data output means for supplying data; address bus means for coupling the addressing means of said processor means to said address means of said memory means; data bus means for coupling the data means of said memory means with the data input means and the data output means of said processor means; and memory accessing means coupled to said address bus means and said data bus means for storing and reading data at addressed locations in the memory means, said memory accessing means including interrupt means coupled to said processor means for suspending execution of operations for a memory access cycle; address specifying means for supplying addresses to said address bus means, data storage means coupled to said data bus means for supplying data to be written to said memory means, data writing means coupled to the data bus for selectively writing data from said data storage means to a memory location specified by said address specifying means, data reading means for causing data to be retrieved from a memory location specified by said address specifying means and coupled to said data bus means, comparing means coupled to said data bus means and to said data storage means for supplying an error signal when data read from a memory location is not the same as the data written to the same memory location, and means responsive to said error signal for stopping operation of said memory access means.

Claim 6

A memory test unit comprising: memory means for storing data and having address means for accessing an addressed location and data means for selectively reading and writing data at an accessed location; processor means for executing predetermined operations and including addressing means for supplying addresses, data input means for accepting data, and data output means for supplying data; address bus means for coupling the addressing means of said processor means to said address means of said memory means; data bus means for coupling the data means of said memory means with the data input means and the data output means of said processor means; and memory accessing means coupled to said address bus means and said data bus means for storing and reading data at addressed locations in the memory means, said memory accessing means including interrupt means coupled to said processor means for suspending execution of operations for a memory access cycle; address specifying means for supplying addresses to said address bus means, data storage means coupled to said data bus means for supplying data to be written to said memory means, data writing means coupled to the data bus for selectively writing data from said data storage means to a memory location specified by said address specifying means, data reading means for causing data to be retrieved from a memory location specified by said address specifying means and coupled to said data bus means, comparing means coupled to said data bus means and to said data storage means for supplying an error signal when data read from a memory location is not the same as the data written to the same memory location, and means responsive to said error signal for stopping operation of said memory access means.

Claim 7

The apparatus as claimed in claim 4 further including in said memory accessing means a means responsive to said comparing means for supplying the error signal to said processor means.