Pulsed ground circuit for CAM and PAL memories

Claim 2

A content addressable memory (CAM), wherein a match line associated with a row of CAM cells indicates a match condition when a value placed on a plurality of bit lines matches a value stored in the row of CAM cells, comprising: a row of match transistors, each match transistor of said row of match transistors coupled at a gate to a match output of a corresponding CAM cell of the row of CAM cells, and said each match transistor coupled at a first terminal to the match line; a match sense line coupled to a second terminal of each match transistor of said row of match transistors, said match sense line carrying a match sense signal, said match sense signal characterized by two different voltages, a sensing voltage and a charging voltage, wherein a voltage level of the match line is sensed when said match sense line is at said sensing voltage to detect a match condition if present; and means for supplying charge to the match line through said match transistors to charge the match line to a quiescent level when said match sense line is at said charging voltage.

Claim 3

A CAM according to claim 1, further comprising: a plurality of rows of CAM cells, each of said plurality of rows of CAM cells containing values which are matched against the value placed on the plurality of bit lines; and a plurality of match lines, each of said plurality of match lines indicating a match condition, if present, for a corresponding row of said plurality of CAM cells.

Claim 4

A CAM according to claim 1, wherein said row of match transistors are NMOS devices.

Claim 5

A CAM according to claim 1, further comprising means for driving said match signal sense line to said charging voltage in response to detecting one of either a match or a mismatch on the match line.

Claim 6

A match sense circuit, wherein a plurality of match lines, each indicating either a match or mismatch in a cell, are input to the match sense circuit, and wherein an output of the match sense circuit indicates a match when all the inputs indicate a match in their corresponding cell and indicates a mismatch when at least one of the inputs indicates a mismatch, the match sense circuit comprising: N match transistors, where N is an integer equal to the number of inputs, with a gate of each match transistor coupled to a corresponding input, wherein current is allowed to flow between a first terminal and second terminal of a match transistor when said input coupled to said gate of said match transistor indicates a mismatch in a corresponding cell; a match line coupled to said first terminals of each of said N match transistors; means coupled to said match line for charging said match line to a charged voltage; a match line current sink coupled to said second terminals of each of said N match transistors, wherein, during a match sense period, a signal voltage on said match line drops from said charged voltage at a rate substantially proportional to the number of said N match transistors which allow current to flow between their first and second terminals; a reference line; means coupled to said reference line for charging said reference line to said charged voltage; a reference line current sink; a reference discharge transistor, coupled between said reference line and said reference line current sink, for discharging, during a match sense period, said reference line to said reference line current sink at a rate less than a discharge of said match line with a single match transistor indicating a mismatch; and a comparator coupled at a signal input to said match line and coupled at a reference input to said reference line, for comparing said signal voltage on said match line with a reference voltage on said reference line, wherein said comparator indicates a mismatch when said signal voltage differs from said reference voltage by more than a predetermined difference threshold voltage.

Claim 7

A match sense circuit, wherein a plurality of match lines, each indicating either a match or mismatch in a cell, are input to the match sense circuit, and wherein an output of the match sense circuit indicates a match when all the inputs indicate a match in their corresponding cell and indicates a mismatch when at least one of the inputs indicates a mismatch, the match sense circuit comprising: N match transistors, where N is an integer equal to the number of inputs, with a gate of each match transistor coupled to a corresponding input, wherein current is allowed to flow between a first terminal and second terminal of a match transistor when said input coupled to said gate of said match transistor indicates a mismatch in a corresponding cell; a match line coupled to said first terminals of each of said N match transistors; means coupled to said match line for charging said match line to a charged voltage; a match line current sink coupled to said second terminals of each of said N match transistors, wherein, during a match sense period, a signal voltage on said match line drops from said charged voltage at a rate substantially proportional to the number of said N match transistors which allow current to flow between their first and second terminals; a reference line; means coupled to said reference line for charging said reference line to said charged voltage; a reference line current sink; a reference discharge transistor, coupled between said reference line and said reference line current sink, for discharging, during a match sense period, said reference line to said reference line current sink at a rate less than a discharge of said match line with a single match transistor indicating a mismatch; and a comparator coupled at a signal input to said match line and coupled at a reference input to said reference line, for comparing said signal voltage on said match line with a reference voltage on said reference line, wherein said comparator indicates a mismatch when said signal voltage differs from said reference voltage by more than a predetermined difference threshold voltage.

Claim 8

The match sense circuit of claim 5, further comprising N reference transistors coupled between said reference line and said reference line current sink to mirror, onto said reference line, capacitive and leakage current effects which are caused by said N match transistors on said match line when inputs to each of said N match transistor hates indicate matches.

Claim 9

The match line sense circuit of claim 5, wherein said match line current sink and said reference line current sink are blocked from sinking current at times other than said match sensing period.

Claim 10

The match sense circuit of claim 7, wherein said match and reference line current sinks are blocked, at said times other than said match sensing period, from sinking current by raising a voltage level of said match and reference line current sinks.