Active matrix display apparatus with plural signal input connections to the supplemental capacitor line

Claim 1

An active matrix display apparatus with reduced signal delay characteristics comprising: pixel electrodes arranged in a matrix fashion on an insulating substrate and enmeshed by generally orthogonal drive lines including a plurality of storage capacitance lines and a plurality of gate bus lines, said storage capacitance lines connected individually to storage capacitance electrodes, said storage capacitance electrodes arranged opposite to said pixel electrodes, a common main line which is connected to said storage capacitance lines and intersects said plurality of gate bus lines, at least one branch line branched from said common main line with the number of branch lines being sufficient to reduce the time delay of signals to said storage capacitance electrodes opposite to said pixel electrodes, the branch line dividing equally said common main line, and a branch terminal formed at the leading end of said at least one branch line, wherein said common main line is adapted to receive at least three electrically driven signal inputs provided to different locations with equal distances therebetween on said common main line, thereby dividing said common main line into at least two drive line segments, and reducing the time delay for signal inputs to reach pixel electrodes located at positions most remote from the ends of the common main line.