Auto-calibrated current-mode digital-to-analog converter and method therefor

Claim 2

A current-mode digital-to-analog converter (DAC), comprising: a first sub-DAC having a plurality of current sample and hold circuits, the first sub-DAC receiving a reference current and a plurality of least-significant-bits of a K-bit digital signal, where K is an integer, and in response, the first sub-DAC providing a first analog signal corresponding to the plurality of least-significant-bits; a second sub-DAC having a plurality of current sample and hold circuits, the second sub-DAC receiving the reference current and a plurality of most-significant-bits of the K-bit digital signal, and in response, the second sub-DAC providing a second analog signal corresponding to the plurality of most significant-bits; an attenuator, coupled to the first sub-DAC, the attenuator attenuating the first analog signal and providing an attenuated first analog signal; a gain adjust sample and hold circuit for adjusting the attenuated first analog signal with a constant scale factor to compensate for device mismatch errors in the attenuator, and providing an adjusted attenuated first analog signal; and a summing element for receiving the adjusted attenuated first analog signal and the second analog signal, and in response, providing an output analog signal.

Claim 3

The current-mode digital-to-analog converter of claim 1, wherein the gain adjust sample and hold circuit receives a calibration current for calibrating the constant scale factor.

Claim 4

The current-mode digital-to-analog converter of claim 2, wherein the gain adjust sample and hold circuit comprises: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a differential amplifier having a first input terminal coupled to the control electrode of the second transistor, a second input terminal coupled to the control electrode of the third transistor, and an output terminal coupled to the gate of the first transistor; a fourth transistor having a first current electrode coupled to the control electrode of the second transistor, a control electrode for receiving a first bias voltage, and a second current electrode; a fifth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrode of the fourth transistor for receiving the first bias voltage, and a second current electrode; first switch means, coupled to the second current electrodes of the second and third transistors, for selectively coupling the attenuated first analog signal to the second current electrodes of the second and third transistors; second switch means for selectively coupling the control electrodes of the second and third transistors to the first and second input terminals, respectively, of the differential amplifier; third switch means for selectively coupling the output terminal of the differential amplifier to the gate of the first transistor; and fourth switch means for selectively coupling the second current electrodes of the second and third transistors to the summing element.

Claim 5

The current-mode digital-to-analog converter of claim 3, further comprising: a sixth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode; a seventh transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode for receiving a second bias voltage, and a second current electrode coupled to the first current electrode of the fourth transistor; an eighth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode connected to the control electrode of the sixth transistor, and a second current electrode; a ninth transistor having a first current electrode coupled to the second current electrode of the eighth transistor, a control electrode coupled to the control electrode of the seventh transistor for receiving the second bias voltage, and a second current electrode coupled to the first current electrode of the fifth transistor; and a differential amplifier having a first input terminal for receiving a common-mode reference voltage, a second input terminal coupled to the first current electrodes of the second and third transistors, and an output terminal coupled to the control electrodes of the sixth and eighth transistors.

Claim 6

The current-mode digital-to-analog converter of claim 3, wherein the first, second, third, sixth, seventh, eighth, and ninth transistors are metal-oxide semiconductor transistors of a first conductivity type, and the fourth and fifth transistors are metal-oxide semiconductor transistors of a second conductivity type.

Claim 7

The current-mode digital-to-analog converter of claim 1, wherein the gain adjust sample and hold circuit is for sampling the attenuated first analog signal, calibrating the constant scale factor, sampling the attenuated first analog signal, and holding and adjusting the attenuated first analog signal for providing the adjusted attenuated first analog signal.

Claim 8

The current-mode digital-to-analog converter of claim 1, further comprising: a third sub-DAC having a plurality of current sample and hold circuits for receiving the reference current and a second plurality of most-significant-bits of the K-bit digital signal, and in response, providing a third analog signal corresponding to the second plurality of most-significant-bits; a second attenuator, coupled to the summing element, for attenuating the output analog signal and providing an attenuated output analog signal; a gain adjust sample and hold circuit for adjusting the attenuated output analog signal with a constant scale factor to compensate for device mismatch errors in the second attenuator, and providing an adjusted attenuated output analog signal; and a second summing element for receiving the adjusted attenuated output analog signal and the third analog signal, and in response, providing a second output analog signal.

Claim 9

An auto-calibrated current-mode digital-to-analog converter (DAC) for converting a K-bit digital signal to an analog signal, comprising: a first sub-DAC for receiving N-bits of the K-bit digital signal, and in response, providing a first analog signal corresponding to the N-bits of the K-bit digital signal; a second sub-DAC for receiving M-bits of the K-bit digital signal, and in response, providing a second analog signal corresponding to the M-bits of the K-bit digital signal; a calibrated attenuator, comprising: an attenuator, coupled to the first sub-DAC, for attenuating the first analog signal and providing an attenuated first analog signal; and a gain adjust sample and hold circuit for adjusting the attenuated first analog signal with a constant scale factor to compensate for device mismatch errors in the attenuator, and providing an adjusted attenuated first analog signal; and a summing element for receiving the adjusted attenuated first analog signal and the second analog signal, and in response, providing an output analog signal.

Claim 10

An auto-calibrated current-mode digital-to-analog converter (DAC) for converting a K-bit digital signal to an analog signal, comprising: a first sub-DAC for receiving N-bits of the K-bit digital signal, and in response, providing a first analog signal corresponding to the N-bits of the K-bit digital signal; a second sub-DAC for receiving M-bits of the K-bit digital signal, and in response, providing a second analog signal corresponding to the M-bits of the K-bit digital signal; a calibrated attenuator, comprising: an attenuator, coupled to the first sub-DAC, for attenuating the first analog signal and providing an attenuated first analog signal; and a gain adjust sample and hold circuit for adjusting the attenuated first analog signal with a constant scale factor to compensate for device mismatch errors in the attenuator, and providing an adjusted attenuated first analog signal; and a summing element for receiving the adjusted attenuated first analog signal and the second analog signal, and in response, providing an output analog signal.

Claim 11

The auto-calibrated current-mode digital-to-analog converter of claim 8, wherein first sub-DAC comprises 2 N +1 equal current elements, the second sub-DAC comprises 2 M +1 equal current elements, each of the current elements receiving a reference current.

Claim 12

The auto-calibrated current-mode digital-to-analog converter of claim 9, further comprising an additional current element, the additional current element for receiving the reference current, and in response, providing a calibrated current to the gain adjust sample and hold circuit for calibrating the constant scale factor.

Claim 13

The auto-calibrated current-mode digital-to-analog converter of claim 10, wherein the equal current elements and the additional current element are each characterized as being current sample and hold circuits.

Claim 14

The auto-calibrated current-mode digital-to-analog converter of claim 8, wherein the gain adjust sample and hold circuit comprises: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a differential amplifier having a first input terminal coupled to the control electrode of the second transistor, a second input terminal coupled to the control electrode of the third transistor, and an output terminal coupled to the gate of the first transistor; a fourth transistor having a first current electrode coupled to the control electrode of the second transistor, a control electrode for receiving a first bias voltage, and a second current electrode; a fifth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrode of the fourth transistor for receiving the first bias voltage, and a second current electrode; first switch means, coupled to the second current electrodes of the second and third transistors, for selectively coupling the attenuated first analog signal to the second current electrodes of the second and third transistors; second switch means for selectively coupling the control electrodes of the second and third transistors to the first and second input terminals, respectively, of the differential amplifier; third switch means for selectively coupling the output terminal of the differential amplifier to the gate of the first transistor; and fourth switch means for selectively coupling the second current electrodes of the second and third transistors to the summing element.

Claim 15

The auto-calibrated current-mode digital-to-analog converter of claim 12, wherein the gain adjust sample and hold circuit further comprising: a sixth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode; a seventh transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode for receiving a second bias voltage, and a second current electrode coupled to the first current electrode of the fourth transistor; an eighth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode connected to the control electrode of the sixth transistor, and a second current electrode; a ninth transistor having a first current electrode coupled to the second current electrode of the eighth transistor, a control electrode coupled to the control electrode of the seventh transistor for receiving the second bias voltage, and a second current electrode coupled to the first current electrode of the fifth transistor; and a differential amplifier having a first input terminal for receiving a common-mode reference voltage, a second input terminal coupled to the first current electrodes of the second and third transistors, and an output terminal coupled to the control electrodes of the sixth and eighth transistors.

Claim 16

The auto-calibrated current-mode digital-to-analog converter of claim 13, wherein the first, second, third, sixth, seventh, eighth, and ninth transistors are metal-oxide semiconductor transistors of a first conductivity type, and the fourth and fifth transistors are metal-oxide semiconductor transistors of a second conductivity type.

Claim 17

The auto-calibrated current-mode digital-to-analog converter of claim 14, wherein the first conductivity type is P-channel, and the second conductivity type is N-channel.

Claim 18

In a current-mode digital-to-analog converter (DAC) for converting a K-bit digital signal to an analog signal, where K is an integer, the DAC comprising a first sub-DAC having a plurality of current elements, a second sub-DAC having a plurality of current elements, and an attenuator, a method for removing device mismatch effects in the attenuator which cause nonlinearity errors in the current-mode digital-to-analog converter, comprising the steps of: providing N-bits of the K-bit digital signal to the first sub-DAC, where N is an integer less than K, and in response, the first sub-DAC providing a first analog signal corresponding to the N-bits of the K-bit digital signal; providing M-bits of the K-bit digital signal to the second sub-DAC, where M is an integer less than K, and in response, the second sub-DAC providing a second analog signal corresponding to the M-bits of the K-bit digital signal; attenuating the first analog signal, and in response, providing an attenuated first analog signal; summing a current from each current element of the plurality of current elements in the first DAC to provide a calibration current; dividing the calibration current by the quantity 2 N minus the mismatch error; sampling the calibration current; calibrating a scale factor, the scale factor for compensating for the nonlinearity error caused by device mismatch; sampling the attenuated first analog signal; and holding and adjusting the attenuated first analog signal with the scale factor for providing an adjusted attenuated first analog signal.

Claim 19

In a current-mode digital-to-analog converter (DAC) for converting a K-bit digital signal to an analog signal, where K is an integer, the DAC comprising a first sub-DAC having a plurality of current elements, a second sub-DAC having a plurality of current elements, and an attenuator, a method for removing device mismatch effects in the attenuator which cause nonlinearity errors in the current-mode digital-to-analog converter, comprising the steps of: providing N-bits of the K-bit digital signal to the first sub-DAC, where N is an integer less than K, and in response, the first sub-DAC providing a first analog signal corresponding to the N-bits of the K-bit digital signal; providing M-bits of the K-bit digital signal to the second sub-DAC, where M is an integer less than K, and in response, the second sub-DAC providing a second analog signal corresponding to the M-bits of the K-bit digital signal; attenuating the first analog signal, and in response, providing an attenuated first analog signal; summing a current from each current element of the plurality of current elements in the first DAC to provide a calibration current; dividing the calibration current by the quantity 2 N minus the mismatch error; sampling the calibration current; calibrating a scale factor, the scale factor for compensating for the nonlinearity error caused by device mismatch; sampling the attenuated first analog signal; and holding and adjusting the attenuated first analog signal with the scale factor for providing an adjusted attenuated first analog signal.

Claim 20

The method of claim 16, further comprising the step of summing the adjusted attenuated first analog signal with the second analog signal.

Claim 21

The method of claim 16, wherein the step of summing a current further comprises summing a current from 2 N +1 equal current elements.

Claim 22

The method of claim 16, wherein the step of providing N-bits of the K-bit digital signal comprises providing a least-significant-bits of the K-bit digital signal to the first sub-DAC.

Claim 23

The method of claim 16, wherein the step of providing M-bits of the K-bit digital signal comprises providing a most-significant-bits of the K-bit digital signal to the second sub-DAC.