US5446450A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Genus tower light controller
Assignee: Sony Electronics Inc
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Filing: 1993-11-04
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Granted: 1995-08-29
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Expires: 2013-11-04
Abstract
Abstract A tower light controller comprises logic circuitry that easily connects with equipment used in the production of semiconductor wafers. The tower light controller uses the existing signals in the production equipment, namely a process signal, an alarm signal, left and right cassette present signals, and left and right atmosphere signals, to appropriately drive a light tower comprised of a yellow lamp, a red lamp, and a green lamp. The logic circuitry turns on the green lamp when a product is being run. A yellow lamp is continuously driven when the equipment has wafers that are ready to be unloaded and the yellow lamp is flashed when the equipment is ready to be loaded with wafers. The red lamp is flashed during alarm conditions and is driven continuously when the equipment is placed in a repair or in a preventative maintenance mode. The logic circuitry also comprises an oscillator formed by a series connection of three inverters. A pair of resistors are connected in series with each other and across the first and third inverters. A capacitor has one terminal connected between the second and the third inverters and the other terminal connected between the two resistors. The circuit additionally comprises a pair of LEDs, reverse biased with respect to each other, connected across the second inverter. With the addition of the two LEDs, the frequency of the oscillating signal may be lowered past the typical floor of 4 to 7 Hz down to about 0.25 Hz.
Inventors
- 👤 Paul Knutson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:44
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/06; H10P72/0612; H10P72/0606
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
218 words
An apparatus for indicating the states of a semiconductor wafer production process, comprising: cassette logic circuitry for generating a first signal that varies depending upon whether wafers are present in a chamber or if said chamber is empty and depending upon whether said chamber is at atmospheric pressure or if said chamber is pumped down to a vacuum; first indicator logic circuitry, connected to said cassette logic circuitry, for receiving said first signal, for continuously driving a first indicator when said chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said chamber has wafers that are ready to be unloaded; second indicator logic circuitry for intermittently driving a second indicator when an alarm signal is received and for continuously driving said second indicator when said production process is placed in an interrupt mode; and third indicator logic circuitry for continuously driving a third indicator when wafers in said chamber are being processed; wherein said second indicator logic circuitry is connected to said first indicator logic circuitry and to said third indicator logic circuitry and prevents said first indicator logic circuitry and said third indicator logic circuitry from respectively driving said first and third indicators whenever said alarm signal is received at said second indicator logic circuitry.
Claim 2
Independent Claim
218 words
An apparatus for indicating the states of a semiconductor wafer production process, comprising: cassette logic circuitry for generating a first signal that varies depending upon whether wafers are present in a chamber or if said chamber is empty and depending upon whether said chamber is at atmospheric pressure or if said chamber is pumped down to a vacuum; first indicator logic circuitry, connected to said cassette logic circuitry, for receiving said first signal, for continuously driving a first indicator when said chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said chamber has wafers that are ready to be unloaded; second indicator logic circuitry for intermittently driving a second indicator when an alarm signal is received and for continuously driving said second indicator when said production process is placed in an interrupt mode; and third indicator logic circuitry for continuously driving a third indicator when wafers in said chamber are being processed; wherein said second indicator logic circuitry is connected to said first indicator logic circuitry and to said third indicator logic circuitry and prevents said first indicator logic circuitry and said third indicator logic circuitry from respectively driving said first and third indicators whenever said alarm signal is received at said second indicator logic circuitry.
Claim 3
Dependent Claim
116 words
An apparatus as set forth in claim 1, wherein: said cassette logic circuitry is also for generating a second signal that varies depending upon whether wafers are present in a second chamber or if said second chamber is empty and depending upon whether said second chamber is at atmospheric pressure or if said second chamber is pumped down to a vacuum; and said first indicator logic circuitry is also for receiving said second signal and for continuously driving said first indicator when said second chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said second chamber has wafers that are ready to be unloaded.
Claim 4
Dependent Claim
83 words
An apparatus as set forth in claim 2, wherein said cassette logic circuitry comprises: a first JK flip-flop for receiving a first atmosphere signal at its clock input and a first cassette present signal at its clear input and for outputting said first signal at its Q output; and a second JK flip-flop for receiving a second atmosphere signal at its clock input and a second cassette present signal at its clear input and for outputting said second signal at its Q output.
Claim 5
Dependent Claim
85 words
An apparatus as set forth in claim 3, wherein said first indicator logic circuitry comprises: an OR gate having said first signal and said second signal as inputs; and means for transmitting an oscillating signal to said first indicator for flashing said first indicator when an output of said OR gate is at a logical value of "1" and for transmitting a constant voltage signal for continuously driving said first indicator when said output of said 0R gate is at a logical value of "0."
Claim 6
Dependent Claim
99 words
An apparatus as set forth in claim 2, wherein said first indicator logic circuitry comprises: a first AND gate having a first cassette present signal and a first atmosphere signal as inputs; a second AND gate having a second cassette present signal and a second atmosphere signal as inputs; a third AND gate having outputs from said first AND gate and second AND gate as inputs; and means for receiving an output of said third AND gate and for turning off said third indicator when said output of said third AND gate is at a logical value of "1."
Claim 7
Dependent Claim
73 words
An apparatus as set forth in claim 2, wherein said second indicator logic circuitry comprises: a first switch for transmitting an oscillating signal to said second indicator for flashing said second indicator when said alarm signal is at a logical value of "1"; and a second switch for transmitting a constant voltage signal to said second indicator for continuously driving said second indicator when said second switch is closed during said interrupt mode.
Claim 8
Dependent Claim
31 words
An apparatus as set forth in claim 1, wherein said first indicator is a yellow lamp, said second indicator is a red lamp, and said third indicator is a green lamp.
Claim 9
Dependent Claim
61 words
An apparatus as set forth in claim 1, wherein said third indicator logic circuitry comprises a switch for receiving a process signal at an input and an inverted alarm signal at a control gate and for passing said process signal through to a relay and to said third indicator whenever said inverted alarm signal is not received at said control gate.
Claim 10
Dependent Claim
43 words
An apparatus as set forth in claim 1, further comprising means for generating an oscillating signal that is used by said first indicator logic circuitry for intermittently driving said first indicator and by second logic indicator circuitry for intermittently driving said second indicator.
Claim 11
Independent Claim
252 words
An apparatus for indicating the states of a semiconductor wafer production process, comprising: cassette logic circuitry for generating a first signal that varies depending upon whether wafers are present in a chamber or if said chamber is empty and depending upon whether said chamber is at atmospheric pressure or if said chamber is pumped down to a vacuum; first indicator logic circuitry, connected to said cassette logic circuitry, for receiving said first signal, for continuously driving a first indicator when said chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said chamber has wafers that are ready to be unloaded; second indicator logic circuitry for intermittently driving a second indicator when an alarm signal is received and for continuously driving said second indicator when said production process is placed in an interrupt mode; third indicator logic circuitry for continuously driving a third indicator when wafers in said chamber are being processed; and means for generating an oscillating signal that is used by said first indicator logic circuitry for intermittently driving said first indicator and by said second indicator logic circuitry for intermittently driving said second indicator; wherein said second indicator logic circuitry is connected to said first indicator logic circuitry and to said third indicator logic circuitry and prevents said first indicator logic circuitry and said third indicator logic circuitry from respectively driving said first and third indicators whenever said alarm signal is received at said second indicator logic circuitry.
Claim 12
Independent Claim
252 words
An apparatus for indicating the states of a semiconductor wafer production process, comprising: cassette logic circuitry for generating a first signal that varies depending upon whether wafers are present in a chamber or if said chamber is empty and depending upon whether said chamber is at atmospheric pressure or if said chamber is pumped down to a vacuum; first indicator logic circuitry, connected to said cassette logic circuitry, for receiving said first signal, for continuously driving a first indicator when said chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said chamber has wafers that are ready to be unloaded; second indicator logic circuitry for intermittently driving a second indicator when an alarm signal is received and for continuously driving said second indicator when said production process is placed in an interrupt mode; third indicator logic circuitry for continuously driving a third indicator when wafers in said chamber are being processed; and means for generating an oscillating signal that is used by said first indicator logic circuitry for intermittently driving said first indicator and by said second indicator logic circuitry for intermittently driving said second indicator; wherein said second indicator logic circuitry is connected to said first indicator logic circuitry and to said third indicator logic circuitry and prevents said first indicator logic circuitry and said third indicator logic circuitry from respectively driving said first and third indicators whenever said alarm signal is received at said second indicator logic circuitry.
Claim 13
Independent Claim
391 words
An apparatus for indicating the states of a semiconductor wafer production process, comprising: cassette logic circuitry for generating a first signal that varies depending upon whether wafers are present in a chamber or if said chamber is empty and depending whether said chamber is at atmospheric pressure or if said chamber is pumped down to a vacuum; first indicator logic circuitry, connected to said cassette logic circuitry, for receiving said first signal, for continuously driving a first indicator when said chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said chamber has wafers that are ready to be unloaded; second indicator logic circuitry for intermittently driving a second indicator when an alarm signal is received and for continuously driving said second indicator when said production process is placed in an interrupt mode; third indicator logic circuitry for continuously driving a third indicator when wafers in said chamber are being processed; and means for generating an oscillating signal that is used by said first indicator logic circuitry for intermittently driving said first indicator and by said second logic indicator circuitry for intermittently driving said second indicator, said oscillating signal generating means comprising: a first inverter, a second inverter, and a third inverter connected in series with each other; a first resistor and a second resistor connected in series with each other and between said first inverter and said third inverter; a capacitor having a first terminal connected between said second inverter and said third inverter and a second terminal connected between said first resistor and said second resistor; a first LED connected across said second inverter; and a second LED connected across said second inverter and being reverse biased with respect to said first LED; wherein said oscillating signal is generated at an output of said third inverter and said first LED and said second LED enable said oscillating signal to have a lower frequency than that possible without said first LED and said second LED; wherein said second indicator logic circuitry is connected to said first indicator logic circuitry and to said third indicator logic circuitry and prevents said first indicator logic circuitry and said third indicator logic circuitry from respectively driving said first and third indicators whenever said alarm signal is received at said second indicator logic circuitry.
Claim 14
Independent Claim
391 words
An apparatus for indicating the states of a semiconductor wafer production process, comprising: cassette logic circuitry for generating a first signal that varies depending upon whether wafers are present in a chamber or if said chamber is empty and depending whether said chamber is at atmospheric pressure or if said chamber is pumped down to a vacuum; first indicator logic circuitry, connected to said cassette logic circuitry, for receiving said first signal, for continuously driving a first indicator when said chamber is ready to be loaded with wafers, and for intermittently driving said first indicator when said first signal indicates that said chamber has wafers that are ready to be unloaded; second indicator logic circuitry for intermittently driving a second indicator when an alarm signal is received and for continuously driving said second indicator when said production process is placed in an interrupt mode; third indicator logic circuitry for continuously driving a third indicator when wafers in said chamber are being processed; and means for generating an oscillating signal that is used by said first indicator logic circuitry for intermittently driving said first indicator and by said second logic indicator circuitry for intermittently driving said second indicator, said oscillating signal generating means comprising: a first inverter, a second inverter, and a third inverter connected in series with each other; a first resistor and a second resistor connected in series with each other and between said first inverter and said third inverter; a capacitor having a first terminal connected between said second inverter and said third inverter and a second terminal connected between said first resistor and said second resistor; a first LED connected across said second inverter; and a second LED connected across said second inverter and being reverse biased with respect to said first LED; wherein said oscillating signal is generated at an output of said third inverter and said first LED and said second LED enable said oscillating signal to have a lower frequency than that possible without said first LED and said second LED; wherein said second indicator logic circuitry is connected to said first indicator logic circuitry and to said third indicator logic circuitry and prevents said first indicator logic circuitry and said third indicator logic circuitry from respectively driving said first and third indicators whenever said alarm signal is received at said second indicator logic circuitry.
Claim 15
Independent Claim
142 words
An apparatus for generating an oscillating signal, comprising: a first inverter, a second inverter, and a third inverter connected in series with each other; a first resistor and a second resistor connected in series with each other and between said first inverter and said third inverter; a capacitor having a first terminal connected between said second inverter and said third inverter and a second terminal connected between said first resistor and said second resistor; a first LED connected across said second inverter; and a second LED connected across said second inverter and being reverse biased with respect to said first LED; wherein said oscillating signal is generated at an output of said third inverter and said first LED and said second LED enable said oscillating signal to have a lower frequency than that possible without said first LED and said second LED.
Claim 16
Independent Claim
142 words
An apparatus for generating an oscillating signal, comprising: a first inverter, a second inverter, and a third inverter connected in series with each other; a first resistor and a second resistor connected in series with each other and between said first inverter and said third inverter; a capacitor having a first terminal connected between said second inverter and said third inverter and a second terminal connected between said first resistor and said second resistor; a first LED connected across said second inverter; and a second LED connected across said second inverter and being reverse biased with respect to said first LED; wherein said oscillating signal is generated at an output of said third inverter and said first LED and said second LED enable said oscillating signal to have a lower frequency than that possible without said first LED and said second LED.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |