Boost converter power supply with reduced losses, control circuit and method therefor

Claim 3

The method of claim 1, further comprising the steps of: during a first portion of said first time period, storing energy of said diode recovery current in a second inductor; during the remainder of said first time period and for a first portion of said second time period, transferring said energy from said second inductor to a capacitor and then back to said second inductor.

Claim 4

A circuit, comprising: an inductor; a switch, said inductor being coupled in series with said switch, current flowing from a first node, through said inductor to a second node, through said switch and to a third node when said switch is conductive; a switch capacitance discharge circuit having a first terminal, a second terminal and a control terminal, said first terminal of said switch capacitance discharge circuit being coupled to said second node; a capacitor; and a diode, an anode of said diode being coupled to said second terminal of said switch capacitance discharge circuit, current flowing through said diode and into said capacitor when said diode is forward biased.

Claim 5

A circuit, comprising: an inductor; a switch, said inductor being coupled in series with said switch, current flowing from a first node, through said inductor to a second node, through said switch and to a third node when said switch is conductive; a switch capacitance discharge circuit having a first terminal, a second terminal and a control terminal, said first terminal of said switch capacitance discharge circuit being coupled to said second node; a capacitor; and a diode, an anode of said diode being coupled to said second terminal of said switch capacitance discharge circuit, current flowing through said diode and into said capacitor when said diode is forward biased.

Claim 6

The circuit of claim 3, wherein said switch is conductive during a first time period, is substantially nonconductive during a second time period, and is conductive during a third time period, said switch capacitance discharge circuit comprising an inductor, said switch having an intrinsic capacitance, said inductor of said switch capacitance discharge circuit storing energy of a diode recovery current which flows in said diode after said switch is turned on to be conductive during said first time period, said energy stored in said switch capacitance discharge circuit being used to discharge said intrinsic capacitance prior to said switch being turned on to be conductive during said third time period.

Claim 7

The circuit of claim 4, wherein said switch capacitance discharge circuit further comprises a capacitor, said energy stored in said inductor of said switch capacitance discharge circuit being transferred to said capacitor of said switch capacitance discharge circuit and then back to said inductor of said switch capacitance discharge circuit prior to said intrinsic capacitance being discharged.

Claim 8

The circuit of claim 3, wherein said switch capacitance discharge circuit comprises: an inductor having a first terminal and a second terminal, said first terminal of said inductor being coupled to said second node, said second terminal of said inductor being coupled to said diode; a capacitor having a first terminal and a second terminal, said first terminal of said capacitor being coupled to said second node; a first diode having a first terminal and a second terminal, said first terminal of said first diode being coupled to said second terminal of said capacitor of said switch capacitance discharge circuit, said second terminal of said first diode being coupled to said second terminal of said inductor of said switch capacitance discharge circuit; a switch having a first terminal, a second terminal and a control terminal, said first terminal of said switch of said switch capacitance discharge circuit being coupled to said second terminal of said capacitor of said switch capacitance discharge circuit, said control terminal of said switch of said switch capacitance discharge circuit being said control terminal of said switch capacitance discharge circuit; and a second diode having a first terminal and second terminal, said first terminal of said second diode being coupled to said second terminal of said switch of said switch capacitance discharge circuit, said second terminal of said second diode being coupled to said second terminal of said inductor of said switch capacitance discharge circuit.

Claim 9

A boost converter, comprising: an inductor; a capacitor; a diode coupled to control a flow of current from said inductor to said capacitor; a switch coupled to control a flow of current through said inductor, said switch having an intrinsic capacitance, said switch being conductive during a first time period, said switch being substantially nonconductive during a second time period; and means for discharging said intrinsic capacitance during said second time period using energy of a diode recovery current flowing in said diode during said first time period.

Claim 10

A boost converter, comprising: an inductor; a capacitor; a diode coupled to control a flow of current from said inductor to said capacitor; a switch coupled to control a flow of current through said inductor, said switch having an intrinsic capacitance, said switch being conductive during a first time period, said switch being substantially nonconductive during a second time period; and means for discharging said intrinsic capacitance during said second time period using energy of a diode recovery current flowing in said diode during said first time period.

Claim 13

The method of claim 8, wherein said generating a pulse width modulated control signal step further comprises the steps of: supplying said first signal to a first input lead of a comparator; and supplying said second signal to a second input lead of said comparator.

Claim 14

A circuit, comprising: a boost converter having a switch, said boost converter having an input current; and a control circuit having an output terminal, said output terminal being coupled to said switch, said control circuit comprising: a ramp generator circuit having in input lead and an output lead; a subtractor circuit having an input lead and an output lead, said input lead being coupled to said input lead of said ramp generator circuit, said subtractor circuit receiving a signal indicative of said input current of said boost converter; and a comparator circuit having a first input lead, a second input lead, and an output lead, said first input lead being coupled to said output lead of said ramp generator circuit, said second input lead being coupled to said output lead of said subtractor circuit, said output lead being coupled to said output terminal of said control circuit.

Claim 15

A circuit, comprising: a boost converter having a switch, said boost converter having an input current; and a control circuit having an output terminal, said output terminal being coupled to said switch, said control circuit comprising: a ramp generator circuit having in input lead and an output lead; a subtractor circuit having an input lead and an output lead, said input lead being coupled to said input lead of said ramp generator circuit, said subtractor circuit receiving a signal indicative of said input current of said boost converter; and a comparator circuit having a first input lead, a second input lead, and an output lead, said first input lead being coupled to said output lead of said ramp generator circuit, said second input lead being coupled to said output lead of said subtractor circuit, said output lead being coupled to said output terminal of said control circuit.

Claim 16

The circuit of claim 10, wherein said boost converter has an output voltage and an input voltage, said ramp generator circuit outputting a ramp signal, said ramp signal having a peak voltage amplitude of amplitude "a", said subtractor circuit outputting a signal having a voltage amplitude substantially proportional to "a-c", "c" being a voltage amplitude substantially proportional to a magnitude of said input current of said boost converter, said comparator circuit outputting a signal having a duty cycle substantially proportional to "(a-c)/a".

Claim 17

The circuit of claim 10, wherein said boost converter generates an output voltage, said control circuit further comprising: a voltage error amplifier circuit having a first input lead and a second input lead, said first input lead of said voltage error amplifier circuit being coupled to receive said output voltage of said boost converter, said second input lead of said voltage error amplifier circuit being coupled to receive a reference voltage.

Claim 18

The circuit of claim 10, wherein said boost converter also has an input voltage, said control circuit further comprising: a correcting circuit having an input lead and an output lead, said input lead coupled to receive said input voltage of said boost converter, said output lead being coupled to said input lead of said ramp generator circuit.

Claim 19

The circuit of claim 10, wherein said boost converter also has an output current, said control circuit further comprising: a correcting circuit having an input lead and an output lead, said input lead coupled to receive said output current of said boost converter, said output lead being coupled to said input lead of said ramp generator circuit.

Claim 20

The circuit of claim 10, wherein said boost converter also has an output current, an output voltage and an input voltage, said control circuit further comprising: a correcting circuit having a first input lead, a second input lead, a third input lead, and an output lead, said first input lead coupled to receive said output current of said boost converter, said second input lead coupled to receive said output voltage of said boost converter, said third input lead coupled to receive said input voltage of said boost converter, said output lead being coupled to said input lead of said ramp generator circuit.

Claim 21

A circuit, comprising: a boost converter having a switch, said boost converter having an input voltage V IN and supplying an output voltage V OUT , said boost converter having an equivalent input resistance; and means for generating a control signal and supplying said control signal to said switch, said control signal having a duty cycle substantially equal to (V OUT -V IN )/V OUT , said means comparing an output voltage of a subtractor circuit to a voltage ramp of peak amplitude proportional to an output voltage error signal, whereby said equivalent input resistance of said boost converter is maintained substantially constant.

Claim 22

A circuit, comprising: a boost converter having a switch, said boost converter having an input voltage V IN and supplying an output voltage V OUT , said boost converter having an equivalent input resistance; and means for generating a control signal and supplying said control signal to said switch, said control signal having a duty cycle substantially equal to (V OUT -V IN )/V OUT , said means comparing an output voltage of a subtractor circuit to a voltage ramp of peak amplitude proportional to an output voltage error signal, whereby said equivalent input resistance of said boost converter is maintained substantially constant.

Claim 23

The circuit of claim 16, wherein said boost converter has an input current, and wherein said output voltage of said subtractor circuit has a magnitude equal to a magnitude of said output voltage error signal minus a magnitude of a signal proportional to said input current of said boost converter.

Claim 24

A pulse width modulator circuit having a voltage signal input terminal, a clock input terminal, and a pulse width modulator signal output terminal, said pulse width modulator circuit comprising: a voltage subtracting circuit having a first input lead and a second input lead, said first input lead being coupled to said voltage signal input terminal of said pulse width modulator circuit; a ramp voltage signal generator having a voltage signal input lead, a clock input lead, and a ramp voltage output lead, said voltage signal input lead of said ramp voltage signal generator being coupled to said input lead of said voltage subtracting circuit, said clock input lead of ramp voltage signal generator being coupled to said clock input terminal of said pulse width modulator circuit; and a voltage comparator having a first input lead, a second input lead, and an output lead, said first input lead of said voltage comparator being coupled to said ramp voltage output lead of said ramp voltage signal generator, said second input lead of said voltage comparator being coupled to said output lead of said voltage subtracting circuit, said output lead of said voltage comparator being coupled to said pulse width modulator signal output terminal of said pulse width modulator circuit.

Claim 25

A pulse width modulator circuit having a voltage signal input terminal, a clock input terminal, and a pulse width modulator signal output terminal, said pulse width modulator circuit comprising: a voltage subtracting circuit having a first input lead and a second input lead, said first input lead being coupled to said voltage signal input terminal of said pulse width modulator circuit; a ramp voltage signal generator having a voltage signal input lead, a clock input lead, and a ramp voltage output lead, said voltage signal input lead of said ramp voltage signal generator being coupled to said input lead of said voltage subtracting circuit, said clock input lead of ramp voltage signal generator being coupled to said clock input terminal of said pulse width modulator circuit; and a voltage comparator having a first input lead, a second input lead, and an output lead, said first input lead of said voltage comparator being coupled to said ramp voltage output lead of said ramp voltage signal generator, said second input lead of said voltage comparator being coupled to said output lead of said voltage subtracting circuit, said output lead of said voltage comparator being coupled to said pulse width modulator signal output terminal of said pulse width modulator circuit.

Claim 26

The pulse width modulator circuit of claim 18 realized as an integrated circuit, said voltage signal input terminal, said clock input terminal, and said pulse width modulator signal output terminal being terminals of said integrated circuit.

Claim 27

The pulse width modulator circuit of claim 18 also having a second voltage signal input terminal, said pulse width modulator circuit further comprising: a voltage error amplifier having in input lead and an output lead, said input lead being coupled to said second voltage signal input terminal, said output lead of said voltage error amplifier being coupled to said second input lead of said voltage subtracting circuit and influencing a voltage on said second input lead of said voltage subtracting circuit.

Claim 28

Using a pulse width modulator circuit to control a switch of a boost converter, said pulse width modulator circuit having a voltage signal input terminal, a clock input terminal, and a pulse width modulator signal output terminal, said pulse width modulator circuit comprising: a voltage subtracting circuit having a first input lead and a second input lead, said first input lead being coupled to said voltage signal input terminal of said pulse width modulator circuit; a ramp voltage signal generator having a voltage signal input lead, a clock input lead, and a ramp voltage output lead, said voltage signal input lead of said ramp voltage signal generator being coupled to said input lead of said voltage subtracting circuit, said clock input lead of ramp voltage signal generator being coupled to said clock input terminal of said pulse width modulator circuit; and a voltage comparator having a first input lead, a second input lead, and an output lead, said first input lead of said voltage comparator being coupled to said ramp voltage output lead of said ramp voltage signal generator, said second input lead of said voltage comparator being coupled to said output lead of said voltage subtracting circuit, said output lead of said voltage comparator being coupled to said pulse width modulator signal output terminal of said pulse width modulator circuit.

Claim 29

Using a pulse width modulator circuit to control a switch of a boost converter, said pulse width modulator circuit having a voltage signal input terminal, a clock input terminal, and a pulse width modulator signal output terminal, said pulse width modulator circuit comprising: a voltage subtracting circuit having a first input lead and a second input lead, said first input lead being coupled to said voltage signal input terminal of said pulse width modulator circuit; a ramp voltage signal generator having a voltage signal input lead, a clock input lead, and a ramp voltage output lead, said voltage signal input lead of said ramp voltage signal generator being coupled to said input lead of said voltage subtracting circuit, said clock input lead of ramp voltage signal generator being coupled to said clock input terminal of said pulse width modulator circuit; and a voltage comparator having a first input lead, a second input lead, and an output lead, said first input lead of said voltage comparator being coupled to said ramp voltage output lead of said ramp voltage signal generator, said second input lead of said voltage comparator being coupled to said output lead of said voltage subtracting circuit, said output lead of said voltage comparator being coupled to said pulse width modulator signal output terminal of said pulse width modulator circuit.

Claim 30

A boost converter, comprising: a first inductor; a first capacitor; a diode coupled to allow a flow of current from said first inductor into said first capacitor when said diode is forward biased; a main switch coupled to control a flow of current through said first inductor, said main switch having an intrinsic capacitance; and means, comprising a second inductor, for discharging said intrinsic capacitance using energy captured approximately when said diode becomes reverse biased, said energy being captured in said second inductor, said second inductor being disposed in series between said diode and said main switch.

Claim 31

A boost converter, comprising: a first inductor; a first capacitor; a diode coupled to allow a flow of current from said first inductor into said first capacitor when said diode is forward biased; a main switch coupled to control a flow of current through said first inductor, said main switch having an intrinsic capacitance; and means, comprising a second inductor, for discharging said intrinsic capacitance using energy captured approximately when said diode becomes reverse biased, said energy being captured in said second inductor, said second inductor being disposed in series between said diode and said main switch.

Claim 32

The boost converter of claim 22, wherein said means further comprises a second capacitor, said energy being initially captured in said second inductor, being subsequently transferred to said second capacitor, and then being transferred back to said second inductor before said intrinsic capacitance is discharged.

Claim 33

The boost converter of claim 22, further comprising a third capacitor, said third capacitor being disposed in parallel with said diode, at least a part of said energy is energy of a current flowing through said third capacitor when said diode becomes reverse biased.

Claim 34

The boost converter of claim 22, wherein at least a part of said energy is energy of a diode recovery current of said diode.

Claim 35

The boost converter of claim 22, wherein said second inductor has a first terminal and a second terminal, said first terminal being substantially directly connected to said main switch, said second terminal being substantially directly connected to said diode.

Claim 36

The circuit of claim 16 realized on an integrated circuit chip, said integrated circuit chip not comprising an X-Y multiplier.