Memory module with address error detection

Claim 1

A memory module, for use in multiples on a bus as a memory system; said memory module comprising a plurality of storage cells that are assigned a range of addresses, an input circuit for receiving a read command and a read address from said bus, and a compare circuit which generates a match signal when said read address is within said assigned address range for said storage cells; wherein said module further includes: a control circuit, coupled to said compare circuit, which responds to said match signal by occasionally executing said read command in a long tame interval on said bus and at all other times executing said read command in a small time interval; a bus transmit circuit, coupled to said control circuit, for sending a control signal on said bus if said control circuit selects said long time interval; and, an error circuit, coupled to said control circuit and said bus, for setting an error flag if said control circuit selects said small time interval and, during that small time interval, said control signal is detected on said bus from another memory module which selects said long time interval in said memory system; whereby an error is detected when two memory modules generate said match signal for a single read command and one memory module executes that read command in said small time interval, while the other memory module executes that read command in said long time interval.