US5444664A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flash memory and a microcomputer
Assignee: Hitachi Ltd
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Filing: 1994-07-13
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Granted: 1995-08-22
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Expires: 2014-07-13
Abstract
Abstract A microcomputer mounted on a single semiconductor chip includes a central processing unit and a nonvolatile flash memory which allows the information to be processed by the central processing unit to be re-programmed by electrical erasing and programming operations. The microcomputer is provided with a normal power supply voltage terminal and a programming power supply voltage terminal and also incorporates a power supply voltage level detection device and an internal voltage boost circuit to decide the re-programming mode for the flash memory according to the level of the voltage supplied and to select between the boost voltage and the external high voltage in performing the erasing and programming of data.
Inventors
- 👤 Kenichi Kuroda
- 👤 Kiyoshi Matsubara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:37
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G11C16/14; G11C16/16; G11C16/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
258 words
A microcomputer comprising: a first power supply terminal for receiving a circuit reference voltage; a second power supply terminal for receiving a first voltage having a first potential difference with respect to the circuit reference voltage; a third power supply terminal for receiving a second voltage having a second potential difference with respect to the circuit reference voltage, the second potential difference being larger than the first potential difference; a central processing unit which receives the circuit reference voltage and the first voltage and operates in response to these voltages; a flash memory having a plurality of memory cells, wherein each of the memory cells includes a source region and a drain region in a semiconductor substrate, a floating gate formed over the source and drain regions with a first oxide film interposed, and a control gate formed over the floating gate with the first oxide film interposed; and a power supply circuit, which includes: a first level detection circuit to decide whether the first voltage supplied to the second power supply terminal is higher than a specified level; a second level detection circuit to decide whether the second voltage supplied to the third power supply terminal is higher than a specified level; a boost circuit to boost the first voltage supplied to the second power supply terminal; and a voltage selection circuit to select either the second voltage supplied to the third power supply terminal or a boost voltage from the first voltage by the boost circuit and to supply the selected voltage to the flash memory.
Claim 2
Dependent Claim
258 words
A microcomputer comprising: a first power supply terminal for receiving a circuit reference voltage; a second power supply terminal for receiving a first voltage having a first potential difference with respect to the circuit reference voltage; a third power supply terminal for receiving a second voltage having a second potential difference with respect to the circuit reference voltage, the second potential difference being larger than the first potential difference; a central processing unit which receives the circuit reference voltage and the first voltage and operates in response to these voltages; a flash memory having a plurality of memory cells, wherein each of the memory cells includes a source region and a drain region in a semiconductor substrate, a floating gate formed over the source and drain regions with a first oxide film interposed, and a control gate formed over the floating gate with the first oxide film interposed; and a power supply circuit, which includes: a first level detection circuit to decide whether the first voltage supplied to the second power supply terminal is higher than a specified level; a second level detection circuit to decide whether the second voltage supplied to the third power supply terminal is higher than a specified level; a boost circuit to boost the first voltage supplied to the second power supply terminal; and a voltage selection circuit to select either the second voltage supplied to the third power supply terminal or a boost voltage from the first voltage by the boost circuit and to supply the selected voltage to the flash memory.
Claim 3
Dependent Claim
30 words
The microcomputer according to claim 1, wherein the power supply circuit includes a voltage generation circuit that generates a fourth voltage used for an erase operation on the flash memory.
Claim 4
Dependent Claim
66 words
The microcomputer according to claim 2, further comprising: a control circuit which generates a control signal to control the voltage selection circuit in such a way as to supply the second voltage to the flash memory when the second level detection circuit decides that the second voltage supplied to the third power supply terminal is higher than the specified level of the second level detection circuit.
Claim 5
Dependent Claim
66 words
The microcomputer according to claim 3, further comprising: a control register which includes a bit representing the state of a detection signal from the first level detection circuit and the second level detection circuit, and a bit specifying which of the second voltage supplied to the third power supply terminal and the boost voltage the voltage selection circuit should select and supply to the flash memory.
Claim 6
Dependent Claim
234 words
A flash memory comprising: a first power supply terminal for receiving a circuit reference voltage; a second power supply terminal for receiving a first voltage having a first potential difference with respect to the circuit reference voltage; a third power supply terminal for receiving a second voltage having a second potential difference with respect to the circuit reference voltage, the second potential difference being larger than the first potential difference; a plurality of memory cells, wherein each of the memory cells includes a source region and a drain region in a semiconductor substrate, a floating gate formed over the source and drain regions with a first oxide film interposed, and a control gate formed over the floating gate with the first oxide film interposed; and a power supply circuit, which includes: a first level detection circuit to decide whether the first voltage supplied to the second power supply terminal is higher than a specified level; a second level detection circuit to decide whether the second voltage supplied to the third power supply terminal is higher than a specified level; a boost circuit to boost the first voltage supplied to the second power supply terminal; and a voltage selection circuit to select either the second voltage supplied to the third power supply terminal or a boost voltage from the first voltage by the boost circuit and to supply the selected voltage to the flash memory.
Claim 7
Dependent Claim
234 words
A flash memory comprising: a first power supply terminal for receiving a circuit reference voltage; a second power supply terminal for receiving a first voltage having a first potential difference with respect to the circuit reference voltage; a third power supply terminal for receiving a second voltage having a second potential difference with respect to the circuit reference voltage, the second potential difference being larger than the first potential difference; a plurality of memory cells, wherein each of the memory cells includes a source region and a drain region in a semiconductor substrate, a floating gate formed over the source and drain regions with a first oxide film interposed, and a control gate formed over the floating gate with the first oxide film interposed; and a power supply circuit, which includes: a first level detection circuit to decide whether the first voltage supplied to the second power supply terminal is higher than a specified level; a second level detection circuit to decide whether the second voltage supplied to the third power supply terminal is higher than a specified level; a boost circuit to boost the first voltage supplied to the second power supply terminal; and a voltage selection circuit to select either the second voltage supplied to the third power supply terminal or a boost voltage from the first voltage by the boost circuit and to supply the selected voltage to the flash memory.
Claim 8
Dependent Claim
31 words
The flash memory according to claim 5, wherein the power supply circuit includes a voltage generation circuit that generates a fourth voltage used for an erase operation on the flash memory.
Claim 9
Dependent Claim
67 words
The flash memory according to claim 6, further comprising: a control circuit which generates a control signal to control the voltage selection circuit in such a way as to supply the second voltage to the flash memory when the second level detection circuit decides that the second voltage supplied to the third power supply terminal is higher than the specified level of the second level detection circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-21 | 1999-02-20 | 1999-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-21 | 2003-02-20 | 2003-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-21 | 2007-02-20 | 2007-08-22 | $7700.00 | Window Closed / Lapsed |