US5444420A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Numerically controlled phase lock loop synthesizer/modulator and method
Assignee: Harris Corp
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Filing: 1994-09-29
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Granted: 1995-08-22
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Expires: 2014-09-29
Abstract
Abstract A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.
Inventors
- 👤 James V. Wernlund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:57
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/085; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2003; H04L27/2021; H04L27/2025
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
89 words
A phase lock loop circuit for locking on a predetermined frequency and phase, the phase having a value from 0 to 2π that need not be constant, the circuit comprising: means for providing a phase of a signal from an oscillator at first periodic intervals; and means for providing corrective signals to said oscillator at said first intervals by comparing the predetermined phase to the oscillator signal phase, said corrective signals adjusting the frequency and the phase of the signal from said oscillator to the predetermined frequency and phase.
Claim 2
Dependent Claim
89 words
A phase lock loop circuit for locking on a predetermined frequency and phase, the phase having a value from 0 to 2π that need not be constant, the circuit comprising: means for providing a phase of a signal from an oscillator at first periodic intervals; and means for providing corrective signals to said oscillator at said first intervals by comparing the predetermined phase to the oscillator signal phase, said corrective signals adjusting the frequency and the phase of the signal from said oscillator to the predetermined frequency and phase.
Claim 3
Dependent Claim
29 words
The circuit of claim 1 wherein said means for providing a phase comprises band pass filter means for filtering the sine and cosine of the signal from said oscillator.
Claim 4
Dependent Claim
27 words
The circuit of claim 2 wherein said means for providing a phase further comprises means for sampling the filtered sine and cosine signals at said first intervals.
Claim 5
Dependent Claim
20 words
The circuit of claim 1 wherein said means for providing corrective signals comprises a comparator for providing phase corrective signals.
Claim 6
Dependent Claim
14 words
The circuit of claim 4 further comprising means for averaging said phase corrective signals.
Claim 7
Dependent Claim
49 words
The circuit of claim 1 wherein said means for providing corrective signals comprises a discriminator for providing frequency corrective signals until a difference between the predetermined frequency and the frequency of the signal from said oscillator is smaller than a predetermined threshold, and for providing phase corrective signals thereafter.
Claim 8
Dependent Claim
14 words
The circuit of claim 6 further comprising means for averaging said frequency corrective signals.
Claim 9
Dependent Claim
81 words
A phase lock loop circuit that can lock from 0 to 2π comprising: a clock input; a voltage controlled oscillator (VCO); a linear phase detector for providing the phase of a signal from said VCO at a first transition of said clock input; a phase generator for providing a comparative phase at said first transition; and a combiner for providing a corrective signal to said VCO by combining the phase of the VCO and the comparative phase at said first transition.
Claim 10
Dependent Claim
81 words
A phase lock loop circuit that can lock from 0 to 2π comprising: a clock input; a voltage controlled oscillator (VCO); a linear phase detector for providing the phase of a signal from said VCO at a first transition of said clock input; a phase generator for providing a comparative phase at said first transition; and a combiner for providing a corrective signal to said VCO by combining the phase of the VCO and the comparative phase at said first transition.
Claim 11
Dependent Claim
40 words
The circuit of claim 8 wherein said linear phase detector is for providing band pass filtered sine and cosine signals related to the signal from said VCO, and for sampling the filtered sine and cosine signals at said first transition.
Claim 12
Dependent Claim
20 words
The circuit of claim 9 further comprising a memory for providing a phase from the sampled sine and cosine signals.
Claim 13
Dependent Claim
23 words
The circuit of claim 8 further comprising a discriminator for evaluating whether said VCO is to be corrected for frequency or phase error.
Claim 14
Dependent Claim
85 words
A phase detector for converting an analog signal from an oscillator to digital signals related to the phase of the analog signal, comprising: a quadrature converter for separating the analog signal into sine and cosine signals; a band pass filter for each of the sine and cosine signals; an analog to digital converter for each of the filtered sine and cosine signals; and a memory for providing digital signals related to the phase of the analog signal upon receipt of digitized sine and cosine signals.
Claim 15
Dependent Claim
85 words
A phase detector for converting an analog signal from an oscillator to digital signals related to the phase of the analog signal, comprising: a quadrature converter for separating the analog signal into sine and cosine signals; a band pass filter for each of the sine and cosine signals; an analog to digital converter for each of the filtered sine and cosine signals; and a memory for providing digital signals related to the phase of the analog signal upon receipt of digitized sine and cosine signals.
Claim 16
Independent Claim
83 words
A method of locking a phase lock loop (PLL) circuit on a variable phase, the method comprising the steps of: (a) providing an instantaneous phase value of a signal from an oscillator at first periodic intervals; and (b) providing phase corrective signals to the oscillator at the first intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase.
Claim 17
Independent Claim
83 words
A method of locking a phase lock loop (PLL) circuit on a variable phase, the method comprising the steps of: (a) providing an instantaneous phase value of a signal from an oscillator at first periodic intervals; and (b) providing phase corrective signals to the oscillator at the first intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase.
Claim 18
Dependent Claim
44 words
The method of claim 13 wherein PLL circuit also locks on a predetermined frequency, and further comprising the steps of: (c) providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.
Claim 19
Dependent Claim
15 words
The method of claim 13 further comprising the step of averaging the phase corrective signals.
Claim 20
Dependent Claim
34 words
The method of claim 15 wherein the averaged phase corrective signals are provided to the oscillator at a rate that is not less than about ten times a bandwidth frequency of the PLL circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-21 | 1999-02-20 | 1999-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-21 | 2003-02-20 | 2003-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-21 | 2007-02-20 | 2007-08-22 | $7700.00 | Window Closed / Lapsed |