Information processing apparatus

Claim 2

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be accessed commonly by said processors; a plurality of address conversion tables for converting a logical address into a physical address; a plurality of address conversion table managing modules each having a directory for managing a corresponding address conversion table in accordance with contents of a logical address and numbers (Nos.) of processors accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; and abnormality processing means for deleting an inoperable processor number (No.) from a directory of an address conversion table managing module in accordance with abnormality information from said processors, wherein said abnormality processing means includes forced clear designating means for designating said inoperable processor No. for deletion from said plurality of address conversion table managing modules, and forced control means of an operable processor, for sending said inoperable processor No. and a directory clear request to said address conversion table control means in accordance with the designation from said forced clear designating means.

Claim 3

An apparatus according to claim 1, further comprising a system control processor for managing the entire system, and wherein said abnormality processing means comprises forced clear designating means for designating said system control processor to delete the specific processor No. from said address conversion table managing means, and forced control means of said system control processor, for sending the specific processor No. and a directory clear request to said address conversion table control means in accordance with the designation from said forced clear designating means.

Claim 4

An apparatus according to claim 1, wherein said abnormality processing means comprises forced control means for receiving abnormality information from said processors and sending the specific processor No. and a directory clear request directly to said address conversion table control means.

Claim 5

An apparatus according to claim 1, wherein said logical address is constituted by a partial space No., a page No., and an intrapage address, and said directories manage said address conversion tables using said partial space Nos.

Claim 6

An apparatus according to claim 1, wherein a No. of accessible processors is constituted by accessible processor designation bits, and said directories manage said address conversion tables using partial space Nos.

Claim 7

An apparatus according to claim 1, wherein said directories are provided in correspondence with said address conversion tables.

Claim 8

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be commonly accessed by said processors; a plurality of address conversion tables for converting a logical address constituted by a partial space number (No.), a page No., and an intrapage address into a physical address; a plurality of address conversion table managing modules each including a directory for a corresponding address conversion table, said directories managing said address conversion tables in accordance with the partial space No. of a logical address and an accessible processor designation bit indicating a processor accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; forced clear designating means for designating an operable processor based on information from said processor managing means to carry out deletion of an inoperable processor No. from said plurality of address conversion table managing modules in accordance with abnormality information from said processors; and forced control means for causing said operable processor to issue a directory clear request to said address conversion table control means in accordance with the designation from said forced clear designating means.

Claim 9

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be commonly accessed by said processors; a plurality of address conversion tables for converting a logical address constituted by a partial space number (No.), a page No., and an intrapage address into a physical address; a plurality of address conversion table managing modules each including a directory for a corresponding address conversion table, said directories managing said address conversion tables in accordance with the partial space No. of a logical address and an accessible processor designation bit indicating a processor accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; forced clear designating means for designating an operable processor based on information from said processor managing means to carry out deletion of an inoperable processor No. from said plurality of address conversion table managing modules in accordance with abnormality information from said processors; and forced control means for causing said operable processor to issue a directory clear request to said address conversion table control means in accordance with the designation from said forced clear designating means.

Claim 10

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be commonly accessed by said processors; a plurality of address conversion tables for converting a logical address constituted by a partial space number (No.), a page No., and an intrapage address into a physical address; a plurality of address conversion table managing modules each having a directory for a corresponding address conversion table, said directories managing said address conversion tables by a partial space No. of a logical address and an accessible processor designation bit indicating processors accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; a system control processor for managing the entire system; forced clear designating means for causing said processor managing means to designate said system control processor to carry out deletion of an inoperable processor No. from said plurality of address conversion table managing modules in accordance with abnormality information from said processors; and forced control means for causing said system control processor to issue a directory clear request of the inoperable processor No. to said address conversion table control means in accordance with the designation from said forced clear designating means.

Claim 11

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be commonly accessed by said processors; a plurality of address conversion tables for converting a logical address constituted by a partial space number (No.), a page No., and an intrapage address into a physical address; a plurality of address conversion table managing modules each having a directory for a corresponding address conversion table, said directories managing said address conversion tables by a partial space No. of a logical address and an accessible processor designation bit indicating processors accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; a system control processor for managing the entire system; forced clear designating means for causing said processor managing means to designate said system control processor to carry out deletion of an inoperable processor No. from said plurality of address conversion table managing modules in accordance with abnormality information from said processors; and forced control means for causing said system control processor to issue a directory clear request of the inoperable processor No. to said address conversion table control means in accordance with the designation from said forced clear designating means.

Claim 12

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be commonly accessed by said processors; a plurality of address conversion tables for converting a logical address constituted by a partial space number (No.), a page No., and an intrapage address into a physical address; a plurality of address conversion table managing modules each having a directory for a corresponding address conversion table, said directories managing said address conversion tables in accordance with the partial space No. of a logical address and an accessible processor designation bit indicating processors accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; and forced control means for causing said processor managing means to issue a directory clear request for deleting an inoperable processor No. from said plurality of address conversion table managing modules to said address conversion table control means in accordance with abnormality information from said processors.

Claim 13

An information processing apparatus comprising: a plurality of processors for performing arithmetic operations for information processing; a memory unit to be commonly accessed by said processors; a plurality of address conversion tables for converting a logical address constituted by a partial space number (No.), a page No., and an intrapage address into a physical address; a plurality of address conversion table managing modules each having a directory for a corresponding address conversion table, said directories managing said address conversion tables in accordance with the partial space No. of a logical address and an accessible processor designation bit indicating processors accessible to said address conversion tables; address conversion table control means for updating said address conversion table managing modules to update contents of said address conversion tables; processor managing means for checking whether each processor is operable; and forced control means for causing said processor managing means to issue a directory clear request for deleting an inoperable processor No. from said plurality of address conversion table managing modules to said address conversion table control means in accordance with abnormality information from said processors.