Abstract A frequency stabilizing circuit for a π/4 QPSK (Quadrature Phase Shift Keying) signal receiver has a voltage controlled oscillator (VCO) for outputting an oscillation signal whose frequency changes in response to a control voltage applied to the VCO. A mixer changes the frequency of an input π/4 shift QPSK signal. A counter measures the frequency of the π/4 shift QPSK signal from the mixer. A timing generator generates, on the basis of the oscillation signal from the VCO, a timing indicative of an interval during which the counter is to measure the frequency. A set data generator generates a frequency signal having a predetermined set frequency. A comparator compares the frequency measured by the counter and the set frequency of the set data generator to thereby output the resulting frequency deviation. A voltage data generator changes voltage data in association with the frequency deviation. A digital-to-analog converter transforms the voltage data to the control voltage. A demodulator demodulates the π/4 shift QPSK signal from the mixer. An integrator adds up phase shifts output from the demodulator over the interval generated by the timing generator. An adder/subtracter selectively increases or decreases the set frequency of the frequency signal output from the data generator in association with a cumulative phase shift produced by the integrator. The circuit is capable of stabilizing the frequency of a π/4 shift QPSK signal receiver even when the mean frequency differs from the carrier frequency due to the offset of data.
A circuit for stabilizing a frequency of a π/4 shift Quadrature Phase Shift Keying (QPSK) signal receiver, comprising: a Voltage Controlled Oscillator (VCO) for outputting an oscillation signal whose frequency changes in response to an analog control voltage applied to said VCO; a mixer having one input connected to said oscillation signal and another input connected to an input π/4 shift QPSK signal, said mixer changing a frequency of said input shift π/4 shift QPSK signal; a counter for measuring the frequency of the π/4 shift QPSK signal output from said mixer; a timing generator having an input connected to said oscillation signal for generating, on the basis of the oscillation signal from said VCO, an output timing signal indicative of an interval during which said counter is to measure the frequency; a set data generator for generating a frequency signal having a predetermined set frequency; a comparator for comparing the frequency measured by said counter and the set frequency of said set data generator to thereby output a resulting frequency deviation signal; a voltage data generator having an input connected to said frequency deviation signal for changing voltage data depending on the frequency deviation signal; a digital-to-analog converter for converting a digital output of said voltage data generator to said analog control voltage; a demodulator connected to an output of said mixer for demodulating the π/4 shift QPSK signal from said mixer; an integrator having one input connected to an output of said demodulator and another input connected to said timing generator, said integrator integrating phase shifts output from said demodulator over said interval generated by said timing generator; and an adder/subtracter interposed between said set data generator and said comparator and responsive to said integrator for selectively increasing or decreasing the set frequency of the frequency signal output from said set data generator depending on a cumulative phase shift produced by said integrator and input to said adder/subtracter.
Claim 2
Dependent Claim
320 words
A circuit for stabilizing a frequency of a π/4 shift Quadrature Phase Shift Keying (QPSK) signal receiver, comprising: a Voltage Controlled Oscillator (VCO) for outputting an oscillation signal whose frequency changes in response to an analog control voltage applied to said VCO; a mixer having one input connected to said oscillation signal and another input connected to an input π/4 shift QPSK signal, said mixer changing a frequency of said input shift π/4 shift QPSK signal; a counter for measuring the frequency of the π/4 shift QPSK signal output from said mixer; a timing generator having an input connected to said oscillation signal for generating, on the basis of the oscillation signal from said VCO, an output timing signal indicative of an interval during which said counter is to measure the frequency; a set data generator for generating a frequency signal having a predetermined set frequency; a comparator for comparing the frequency measured by said counter and the set frequency of said set data generator to thereby output a resulting frequency deviation signal; a voltage data generator having an input connected to said frequency deviation signal for changing voltage data depending on the frequency deviation signal; a digital-to-analog converter for converting a digital output of said voltage data generator to said analog control voltage; a demodulator connected to an output of said mixer for demodulating the π/4 shift QPSK signal from said mixer; an integrator having one input connected to an output of said demodulator and another input connected to said timing generator, said integrator integrating phase shifts output from said demodulator over said interval generated by said timing generator; and an adder/subtracter interposed between said set data generator and said comparator and responsive to said integrator for selectively increasing or decreasing the set frequency of the frequency signal output from said set data generator depending on a cumulative phase shift produced by said integrator and input to said adder/subtracter.