Self-calibration timing circuit

Claim 1

An apparatus for determining the optimal operating speed of a semiconductor die, comprising: a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a reference clock operating at a reference frequency; means for calculating a ratio of the relaxation oscillator frequency and the reference clock frequency; and means for determining a system clock frequency from the ratio at which the semiconductor die operates in substantially the most efficient and reliable manner.

Claim 2

An apparatus for determining the optimal operating speed of a semiconductor die, comprising: a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a reference clock operating at a reference frequency; means for calculating a ratio of the relaxation oscillator frequency and the reference clock frequency; and means for determining a system clock frequency from the ratio at which the semiconductor die operates in substantially the most efficient and reliable manner.

Claim 4

An apparatus for optimizing operating speed of a semiconductor die, comprising: a relaxation oscillator having a frequency output, said oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a system clock operating at a system clock frequency and having selectable fast and slow speeds, both speeds lower in frequency than the relaxation oscillator frequency; a reference clock having a reference output frequency; a gated counter having clock and gate inputs, said gated counter having a storage register for storing and outputting a signal indicating either a low or a high count in said counter; said gated counter clock input connected to said relaxation oscillator output; said gated counter gate input connected to said reference clock; said gated counter determining a ratio by counting the number of cycles of the relaxation oscillator frequency during at least one period of the reference clock frequency; said gated counter outputting a high count signal to said storage register if the ratio is greater than a predetermined value; and said storage register output controlling the selection of said system clock speed so that a fast clock speed is selected when there is a high count in said storage register.

Claim 5

An apparatus for optimizing operating speed of a semiconductor die, comprising: a relaxation oscillator having a frequency output, said oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a system clock operating at a system clock frequency and having selectable fast and slow speeds, both speeds lower in frequency than the relaxation oscillator frequency; a reference clock having a reference output frequency; a gated counter having clock and gate inputs, said gated counter having a storage register for storing and outputting a signal indicating either a low or a high count in said counter; said gated counter clock input connected to said relaxation oscillator output; said gated counter gate input connected to said reference clock; said gated counter determining a ratio by counting the number of cycles of the relaxation oscillator frequency during at least one period of the reference clock frequency; said gated counter outputting a high count signal to said storage register if the ratio is greater than a predetermined value; and said storage register output controlling the selection of said system clock speed so that a fast clock speed is selected when there is a high count in said storage register.

Claim 8

An apparatus for optimizing the operating speed of a semiconductor die, comprising: a relaxation oscillator having a frequency output, said oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a system clock operating at a system clock frequency and having a plurality of selectable speeds, all lower in frequency than the relaxation oscillator frequency; a system clock speed controller, said controller selecting the speed of said system clock; a reference clock having a reference output frequency; a gated counter having clock and gate inputs and having an output; said gated counter clock input connected to said relaxation oscillator output; said gated counter gate input connected to said reference clock; said gated counter determining a ratio by counting the number of cycles of the relaxation oscillator frequency during at least one period of the reference clock frequency; and said gated counter output connected to said speed controller and outputting the ratio so that said speed controller may determine an optimal system clock speed.

Claim 9

An apparatus for optimizing the operating speed of a semiconductor die, comprising: a relaxation oscillator having a frequency output, said oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a system clock operating at a system clock frequency and having a plurality of selectable speeds, all lower in frequency than the relaxation oscillator frequency; a system clock speed controller, said controller selecting the speed of said system clock; a reference clock having a reference output frequency; a gated counter having clock and gate inputs and having an output; said gated counter clock input connected to said relaxation oscillator output; said gated counter gate input connected to said reference clock; said gated counter determining a ratio by counting the number of cycles of the relaxation oscillator frequency during at least one period of the reference clock frequency; and said gated counter output connected to said speed controller and outputting the ratio so that said speed controller may determine an optimal system clock speed.

Claim 13

A method for optimizing the operating speed of a semiconductor die, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; determining the frequency of the relaxation oscillator; determining the frequency of a reference oscillator; calculating a ratio of the relaxation oscillator and reference oscillator frequencies; and selecting a system clock frequency from the calculated ratio, wherein the semiconductor die operates in substantially the most efficient and reliable manner.

Claim 14

A method for optimizing the operating speed of a semiconductor die, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; determining the frequency of the relaxation oscillator; determining the frequency of a reference oscillator; calculating a ratio of the relaxation oscillator and reference oscillator frequencies; and selecting a system clock frequency from the calculated ratio, wherein the semiconductor die operates in substantially the most efficient and reliable manner.

Claim 17

A method for testing the speed at which a semiconductor die can reliably operate, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the integrated circuit die and operating at a natural frequency thereof; counting the number of cycles of the relaxation oscillator frequency during at least one period of a reference clock frequency so that a ratio is determined between the relaxation oscillator frequency and the reference clock frequency; and outputting the ratio so that a maximum reliable operating speed of the integrated circuit may be determined.

Claim 18

A method for testing the speed at which a semiconductor die can reliably operate, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the integrated circuit die and operating at a natural frequency thereof; counting the number of cycles of the relaxation oscillator frequency during at least one period of a reference clock frequency so that a ratio is determined between the relaxation oscillator frequency and the reference clock frequency; and outputting the ratio so that a maximum reliable operating speed of the integrated circuit may be determined.

Claim 19

A system for testing the speed at which a semiconductor die can reliably operate, said system comprising: a semiconductor integrated circuit die having a relaxation oscillator disposed thereon and operating at a natural frequency thereof; a frequency counter connected to the relaxation oscillator and determining the frequency thereof; and a lookup table for determining the maximum reliable operating speed of the semiconductor integrated circuit die from the relaxation oscillator frequency.

Claim 20

A system for testing the speed at which a semiconductor die can reliably operate, said system comprising: a semiconductor integrated circuit die having a relaxation oscillator disposed thereon and operating at a natural frequency thereof; a frequency counter connected to the relaxation oscillator and determining the frequency thereof; and a lookup table for determining the maximum reliable operating speed of the semiconductor integrated circuit die from the relaxation oscillator frequency.

Claim 23

A system for testing the speed at which a semiconductor die can reliably operate, said system comprising: a semiconductor integrated circuit die having a relaxation oscillator disposed thereon and operating at a natural frequency thereof; a system clock having a plurality of selectable frequencies, all lower in frequency than the relaxation oscillator; a reference clock having a reference output frequency; a gated counter having clock and gate inputs and having an output; said gated counter clock input connected to said relaxation oscillator; said gated counter gate input connected to said reference clock; said gated counter counting the number of cycles of the relaxation oscillator frequency during at least one period of the frequency of said reference clock so that a ratio is determined between the relaxation oscillator frequency and the reference clock frequency; and said gated counter output outputting the ratio so that a maximum reliable operating speed of the semiconductor die may be determined from the ratio.

Claim 24

A system for testing the speed at which a semiconductor die can reliably operate, said system comprising: a semiconductor integrated circuit die having a relaxation oscillator disposed thereon and operating at a natural frequency thereof; a system clock having a plurality of selectable frequencies, all lower in frequency than the relaxation oscillator; a reference clock having a reference output frequency; a gated counter having clock and gate inputs and having an output; said gated counter clock input connected to said relaxation oscillator; said gated counter gate input connected to said reference clock; said gated counter counting the number of cycles of the relaxation oscillator frequency during at least one period of the frequency of said reference clock so that a ratio is determined between the relaxation oscillator frequency and the reference clock frequency; and said gated counter output outputting the ratio so that a maximum reliable operating speed of the semiconductor die may be determined from the ratio.

Claim 25

An apparatus for maintaining an optimal temperature of a semiconductor die, comprising: a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a frequency counter for calculating the frequency of said relaxation oscillator; a temperature sensor in thermal communication with the semiconductor die for determining the temperature thereof; a heat pump in thermal communication with the semiconductor die for maintaining the die at a certain temperature; a temperature controller connected to the temperature sensor and heat pump, said temperature controller controlling the temperature of the semiconductor die to substantially the certain temperature; and a means for determining the certain temperature from the frequency of said relaxation oscillator, wherein at that certain temperature the semiconductor die operates in substantially the most efficient and reliable manner.

Claim 26

An apparatus for maintaining an optimal temperature of a semiconductor die, comprising: a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a frequency counter for calculating the frequency of said relaxation oscillator; a temperature sensor in thermal communication with the semiconductor die for determining the temperature thereof; a heat pump in thermal communication with the semiconductor die for maintaining the die at a certain temperature; a temperature controller connected to the temperature sensor and heat pump, said temperature controller controlling the temperature of the semiconductor die to substantially the certain temperature; and a means for determining the certain temperature from the frequency of said relaxation oscillator, wherein at that certain temperature the semiconductor die operates in substantially the most efficient and reliable manner.

Claim 28

A method for maintaining an optimal operating temperature of a semiconductor die, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; determining the frequency of the relaxation oscillator; measuring the temperature of the semiconductor die; calculating a certain temperature from the measured temperature of the semiconductor die and frequency of the relaxation oscillator; and controlling the temperature of the semiconductor die to substantially the certain temperature, wherein the semiconductor die operates at substantially the most efficient and reliable operating temperature.

Claim 29

A method for maintaining an optimal operating temperature of a semiconductor die, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; determining the frequency of the relaxation oscillator; measuring the temperature of the semiconductor die; calculating a certain temperature from the measured temperature of the semiconductor die and frequency of the relaxation oscillator; and controlling the temperature of the semiconductor die to substantially the certain temperature, wherein the semiconductor die operates at substantially the most efficient and reliable operating temperature.

Claim 30

An apparatus for adjusting interface timing parameters so as to maintain compatibility between different types of semiconductor devices during setup and hold times, comprising: a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a reference clock operating at a reference frequency; means for calculating a ratio of the relaxation oscillator frequency and the reference clock frequency; and means for determining system timing parameters from the ratio so that semiconductor devices having different setup and hold time requirements are compatible.

Claim 31

An apparatus for adjusting interface timing parameters so as to maintain compatibility between different types of semiconductor devices during setup and hold times, comprising: a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; a reference clock operating at a reference frequency; means for calculating a ratio of the relaxation oscillator frequency and the reference clock frequency; and means for determining system timing parameters from the ratio so that semiconductor devices having different setup and hold time requirements are compatible.

Claim 32

A method for adjusting interface timing parameters so as to maintain compatibility between different types of semiconductor devices during setup and hold times, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; determining the frequency of the relaxation oscillator; determining the frequency of a reference oscillator; calculating a ratio of the relaxation oscillator frequency and the reference clock frequency; and determining system timing parameters from the ratio so that semiconductor devices having different setup and hold time requirements are compatible.

Claim 33

A method for adjusting interface timing parameters so as to maintain compatibility between different types of semiconductor devices during setup and hold times, comprising the steps of: generating a frequency with a relaxation oscillator disposed on the semiconductor die and operating at a natural frequency thereof; determining the frequency of the relaxation oscillator; determining the frequency of a reference oscillator; calculating a ratio of the relaxation oscillator frequency and the reference clock frequency; and determining system timing parameters from the ratio so that semiconductor devices having different setup and hold time requirements are compatible.