US5436178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making semiconductor device including MOS type field effect transistor
Assignee: Renesas Electronics Corp
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Filing: 1994-01-26
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Granted: 1995-07-25
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Expires: 2014-01-26
Abstract
Abstract A semiconductor device includes an MOS field effect transistor having a structure in which the tops of its source/drain regions are covered with a polycrystalline silicon layer. The impurity concentration distribution in its depth direction of the source/drain regions of the MOS field effect transistor is such that the concentration is sufficiently high in an area necessary to have conductivity a prescribed depth away from the surface of the semiconductor substrate, and the impurity concentration drastically decreases in areas deeper than that. Thus, a punch through phenomenon in positions relatively deep in the channel region is suppressed, and an MOS field effect transistor having its channel length reduced to 0.5 μm and less and achieving high performance can be obtained. Such an MOS field effect transistor can be produced by implanting an impurity a number of times, controlling appropriately the peak value and the peak position of the impurity concentration, before and after or only after the formation of the polycrystalline silicon layer.
Inventors
- 👤 Hiroshi Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:52
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D62/60
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
133 words
A manufacturing method of a semiconductor device including a MOS field effect transistor, comprising the steps of: forming a gate electrode on the main surface of a semiconductor substrate with a gate insulating film therebetween; implanting an impurity of a first conductivity type in said semiconductor substrate to form source/drain regions; forming a polycrystalline silicon layer so as to cover the surfaces of said source/drain regions located in the positions interposing a channel region of a second conductivity type therebetween which is positioned in the surface of said semiconductor substrate under said gate electrode; implanting an impurity of said first conductivity type into said polycrystalline silicon layer and into said source/drain regions so that the peak of the concentration distribution of the impurity in the depth direction is within said polycrystalline silicon layer.
Claim 2
Dependent Claim
133 words
A manufacturing method of a semiconductor device including a MOS field effect transistor, comprising the steps of: forming a gate electrode on the main surface of a semiconductor substrate with a gate insulating film therebetween; implanting an impurity of a first conductivity type in said semiconductor substrate to form source/drain regions; forming a polycrystalline silicon layer so as to cover the surfaces of said source/drain regions located in the positions interposing a channel region of a second conductivity type therebetween which is positioned in the surface of said semiconductor substrate under said gate electrode; implanting an impurity of said first conductivity type into said polycrystalline silicon layer and into said source/drain regions so that the peak of the concentration distribution of the impurity in the depth direction is within said polycrystalline silicon layer.
Claim 3
Dependent Claim
54 words
The manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 1, further comprising a step of forming an insulating film for covering the top and sidewalls of said gate electrode between said step of forming said gate electrode and said step of forming said polycrystalline silicon layer.
Claim 4
Dependent Claim
61 words
The manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 2, wherein said step of controlling said impurity concentration distribution includes a step of implanting an impurity into the surface of said semiconductor substrate, using said gate electrode and said insulating film as masks, prior to a step of forming said polycrystalline silicon layer.
Claim 5
Dependent Claim
65 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 3, wherein said step of implanting the impurity into the surface of said semiconductor substrate, using said gate electrode and said insulating film as masks is conducted by implanting arsenic at an implantation energy of about 350 KeV, in a dose of about 5×10 14 /cm 2 .
Claim 6
Dependent Claim
63 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 1, wherein said step of controlling the impurity concentration distribution includes a step of implanting arsenic into said polycrystalline silicon layer at an implantation energy of about 60 KeV, in a dose of about 10 16 /cm 2 after the formation of said polycrystalline silicon layer.
Claim 7
Dependent Claim
40 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 1 further comprising a step of thermal treatment for activating the implanted impurity, only after said step of controlling the impurity concentration distribution.
Claim 8
Dependent Claim
109 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 2 wherein said step of controlling the impurity concentration distribution includes the steps of: implanting arsenic into the surface of said semiconductor substrate at an implantation energy of about 350KeV, in a dose of about 5×10 14 /cm 2 , using said gate electrode and said insulating film as masks, prior to said step of forming said polycrystalline silicon layer; and implanting arsenic into said polycrystalline silicon layer at an implantation energy of about 60 KeV, in a dose 10 16 /cm 2 , after the formation of said polycrystalline silicon layer.
Claim 9
Dependent Claim
40 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 7 further comprising a step of thermal treatment for activating the implanted impurity only after said step of controlling the impurity concentration distribution.
Claim 10
Dependent Claim
152 words
A manufacturing method of a semiconductor device including a MOS field effect transistor, comprising the steps of: forming a gate electrode on the main surface of a semiconductor substrate with a gate insulating film therebetween; forming a polycrystalline silicon layer so as to cover the surface of source/drain regions interposing a channel region of a first conductivity type therebetween which is positioned in the surface of said semiconductor substrate under said gate electrode; and implanting an impurity of a second conductivity type a plurality of times into said polycrystalline silicon layer and said source/drain regions only after the step of forming said polycrystalline silicon layer and changing an implantation energy and a dose for each implantation so that the peak of the impurity concentration distribution in the depth direction is within the range of depth whose resistance is needed to be kept low in said polycrystalline silicon layer or said source/drain regions.
Claim 11
Dependent Claim
152 words
A manufacturing method of a semiconductor device including a MOS field effect transistor, comprising the steps of: forming a gate electrode on the main surface of a semiconductor substrate with a gate insulating film therebetween; forming a polycrystalline silicon layer so as to cover the surface of source/drain regions interposing a channel region of a first conductivity type therebetween which is positioned in the surface of said semiconductor substrate under said gate electrode; and implanting an impurity of a second conductivity type a plurality of times into said polycrystalline silicon layer and said source/drain regions only after the step of forming said polycrystalline silicon layer and changing an implantation energy and a dose for each implantation so that the peak of the impurity concentration distribution in the depth direction is within the range of depth whose resistance is needed to be kept low in said polycrystalline silicon layer or said source/drain regions.
Claim 12
Dependent Claim
54 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 9, further comprising a step of forming an insulting film for covering the top and sidewalls of said gate electrode between said step of forming the gate electrode and said step of forming said polycrystalline silicon layer.
Claim 13
Dependent Claim
97 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 9, wherein said step of controlling the impurity concentration distribution includes; a first impurity implantation step of implanting an impurity of the second conductivity type so that the concentration distribution of the impurity comes to its peak in a position a prescribed depth from the surface of said semiconductor substrate, and a second impurity implantation step of implanting an impurity of the second conductivity type so that the peak of the concentration distribution is positioned in said polycrystalline silicon layer.
Claim 14
Dependent Claim
40 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 11 further comprising a step of thermal treatment for activating the implanted impurity only after said step of controlling the impurity concentration distribution.
Claim 15
Dependent Claim
71 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 11, wherein said step of controlling the impurity concentration distribution further includes a third impurity implantation step of implanting an impurity of the second conductivity type so that the peak of the impurity concentration distribution is positioned between the peaks of the impurity concentration distribution formed by said first and second impurity implantation steps.
Claim 16
Dependent Claim
39 words
A manufacturing method of a semiconductor device including a MOS field effect transistor as recited in claim 13 further comprising a step of thermal treatment for activating the implanted impurity after said step of controlling the impurity concentration distribution.
Claim 17
Dependent Claim
165 words
A manufacturing method of a semiconductor device including a MOS field effect transistor, comprising the steps of: forming a gate electrode on the main surface of a semiconductor substrate with a gate insulating film therebetween; implanting an impurity of a first conductivity type in said semiconductor substrate to form source/drain regions, whereby the peak of the concentration distribution of the impurity in the depth direction is within said substrate; forming a polycrystalline silicon layer so as to cover the surfaces of said source/drain regions located in the positions interposing a channel region of a second conductivity type therebetween which is positioned in the surface of said semiconductor substrate under said gate electrode; and implanting the impurity of said first conductivity type into said polycrystalline silicon layer and into said source/drain region so that the peak of the concentration distribution of the impurity in the depth direction is greater than said peak of the concentration distribution of the impurity formed by said implantation forming source/drain regions.
Claim 18
Dependent Claim
165 words
A manufacturing method of a semiconductor device including a MOS field effect transistor, comprising the steps of: forming a gate electrode on the main surface of a semiconductor substrate with a gate insulating film therebetween; implanting an impurity of a first conductivity type in said semiconductor substrate to form source/drain regions, whereby the peak of the concentration distribution of the impurity in the depth direction is within said substrate; forming a polycrystalline silicon layer so as to cover the surfaces of said source/drain regions located in the positions interposing a channel region of a second conductivity type therebetween which is positioned in the surface of said semiconductor substrate under said gate electrode; and implanting the impurity of said first conductivity type into said polycrystalline silicon layer and into said source/drain region so that the peak of the concentration distribution of the impurity in the depth direction is greater than said peak of the concentration distribution of the impurity formed by said implantation forming source/drain regions.
References Cited (Backward Citations)
US4992389A
Cited
JPS627703A
Cited
US4843023A
Cited
US4914500A
Cited
US5177571A
Cited
US5141891A
Cited
US5024959A
Cited
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