US5434446A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parasitic capacitance cancellation circuit
Assignee: Analog Devices Inc
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Filing: 1994-08-08
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Granted: 1995-07-18
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Expires: 2014-08-08
Abstract
Abstract A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.
Inventors
- 👤 Edward B. Hilton
- 👤 Robert A. Duris
- 👤 Douglas W. Babcock
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:54
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
100 words
A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit comprising: transistor means having an output and including at least one transistor fabricated silicon-on-insulator a silicon substrate region outside the transistor means having a parasitic capacitance to be cancelled; a bootstrap terminal connected to said region outside the transistor means; and a unity gain buffer, responsive to the output of said transistor means and having its output connected to said boot strap terminal for providing a voltage to said region outside the transistor means which follows the voltage developed on the parasitic capacitance thereby nullifying the parasitic capacitance.
Claim 2
Dependent Claim
100 words
A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit comprising: transistor means having an output and including at least one transistor fabricated silicon-on-insulator a silicon substrate region outside the transistor means having a parasitic capacitance to be cancelled; a bootstrap terminal connected to said region outside the transistor means; and a unity gain buffer, responsive to the output of said transistor means and having its output connected to said boot strap terminal for providing a voltage to said region outside the transistor means which follows the voltage developed on the parasitic capacitance thereby nullifying the parasitic capacitance.
Claim 3
Dependent Claim
20 words
The parasitic capacitance cancellation circuit of claim 1 in which the parasitic capacitance includes the metal to substrate parasitic capacitance.
Claim 4
Dependent Claim
20 words
The parasitic capacitance cancellation circuit of claim 1 in which the parasitic capacitance includes sidewall to transistor means parasitic capacitance.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |