Advanced asyncronous video architecture

Claim 2

An asynchronous video system, the system including a memory clock and a video clock, the system comprising: a video memory containing pixel data; means, coupled to the memory clock, for fetching pixel data within the video memory; means coupled to the memory clock for providing a plurality of raster display control signals; FIFO means for receiving the pixel data from the video memory and the raster display control signals from the providing means responsive to a signal from the memory clock such that the raster display control signals and pixel data are in a predetermined relationship defined by the memory clock; and means for processing the display control signals and pixel data from the FIFO means responsive to a signal from the video clock.

Claim 3

The system of claim 1 in which the providing means is a raster display control circuit.

Claim 4

The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a CRT monitor.

Claim 5

The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a flat panel display device.

Claim 6

The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a liquid crystal display device (LCD).

Claim 7

The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes an electroluminant display device (ELD).

Claim 8

The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a plasma display device.

Claim 9

The system of claim 2 in which the raster display control circuit provides advanced control signals.

Claim 10

The system of claim 8 in which the advanced control signals comprise horizontal synchronization (HSYNC), vertical synchronization (VSYNC), BLANK, display enable (DISPEN), cursor on (CURSON) signals.

Claim 11

The system of claim 2 in which the synchronization between the memory control and the display control is achieved by locking the two circuits with the memory clock.

Claim 12

The system of claim 1 in which the providing means is a CRT control circuit.

Claim 13

The system of claim 1 in which the processing means comprises a video process circuit.

Claim 14

The system of claim 12 in which the video process circuit provides at an output responsive to a video clock signal pixel data and raster display control signals.

Claim 15

The system of claim 12 in which the video process circuit provides at output responsive to a video clock signal pixel data, HSYNC control signal, VSYNC control signal, BLANK control signal, DISPEN control signal and CURSON control signal.

Claim 16

The system of claim 1 in which the pixel data fetching means is a video memory control circuit.

Claim 17

The system of claim 15 in which the providing means lacks a synchronization circuit between the video memory control circuit and the display control circuit.

Claim 18

The system of claim 15 in which the synchronization between the memory control and the display control is achieved by locking the two circuits with the memory clock.

Claim 19

The system of claim 1 in which the providing means is a flat panel control circuit.

Claim 20

The system of claim 18 in which the providing means is for split panel control giving one line of data to each section one at a time.

Claim 21

An asynchronous video system, the system including a memory clock and a video clock, the system comprising: a video memory containing pixel data; memory control circuit coupled to the memory clock for fetching pixel data within the video memory; raster display control circuit coupled to the memory clock for providing advanced video control signals, the advanced control signals including HYSNC, VSYNC, BLANK, DISPEN, CURSON control signals and other raster display control signals for a flat panel display device; a FIFO circuit for receiving the pixel data from the memory control circuit and for receiving the advanced display control signals from the raster display control circuit and responsive to a signal from the memory clock providing the pixel data and advanced control signals at an output of the FIFO circuit in a predetermined relationship defined by the memory clock; and a video process circuit for processing the advanced display control signals and the pixel data from the FIFO circuit responsive to a signal from the video clock.

Claim 22

An asynchronous video system, the system including a memory clock and a video clock, the system comprising: a video memory containing pixel data; memory control circuit coupled to the memory clock for fetching pixel data within the video memory; raster display control circuit coupled to the memory clock for providing advanced video control signals, the advanced control signals including HYSNC, VSYNC, BLANK, DISPEN, CURSON control signals and other raster display control signals for a flat panel display device; a FIFO circuit for receiving the pixel data from the memory control circuit and for receiving the advanced display control signals from the raster display control circuit and responsive to a signal from the memory clock providing the pixel data and advanced control signals at an output of the FIFO circuit in a predetermined relationship defined by the memory clock; and a video process circuit for processing the advanced display control signals and the pixel data from the FIFO circuit responsive to a signal from the video clock.

Claim 23

An asynchronous video system for placing pixel data on a display comprising: a memory clock defining a series of memory cycles; a video memory containing pixel data; a memory control circuit, responsive to said memory clock, for causing pixel data to be output from said video memory synchronously with said memory clock; a display control circuit, responsive to said memory clock, for generating a plurality of raster display control signals synchronous with said memory clock; a first-in-first-out (FIFO) circuit, responsive to said memory clock, for receiving said pixel data from said video memory and said plurality of raster display control signals from said display control circuit synchronously with said memory clock; a video clock defining a series of video cycles; and a video processing circuit, coupled to said FIFO and responsive to said video clock, for receiving said pixel data and said plurality of raster display control signals from said FIFO and outputting said pixel data and said plurality of raster display control signals to said display synchronously with said video clock.

Claim 24

An asynchronous video system for placing pixel data on a display comprising: a memory clock defining a series of memory cycles; a video memory containing pixel data; a memory control circuit, responsive to said memory clock, for causing pixel data to be output from said video memory synchronously with said memory clock; a display control circuit, responsive to said memory clock, for generating a plurality of raster display control signals synchronous with said memory clock; a first-in-first-out (FIFO) circuit, responsive to said memory clock, for receiving said pixel data from said video memory and said plurality of raster display control signals from said display control circuit synchronously with said memory clock; a video clock defining a series of video cycles; and a video processing circuit, coupled to said FIFO and responsive to said video clock, for receiving said pixel data and said plurality of raster display control signals from said FIFO and outputting said pixel data and said plurality of raster display control signals to said display synchronously with said video clock.