Digital phase comparator and phase-locked loop

Claim 2

A digital phase comparator (10) comprising: a first flip-flop (11) which is settable by a given phase transition of a first signal (S1) and resettable by a given phase transition of a second signal (S2), and a first counter (13) which is enabled by the flip-flop (11) as long as the latter is set, and whose clock input (ck) is supplied with a clock signal (T) whose frequency is high compared with the frequencies of the first signal (S1) and the second signal (S2), characterized in that a second flip-flop (12) is provided which is settable by a given phase transition of a third signal (S3) and is resettable together with the first flip-flop (11) using the signal (S2), a second counter (14) is provided which is enabled by the second flip-flop (12) as long as the latter is set, and whose clock input (ck) is supplied with the clock signal (T), an evaluation unit (17) is provided which forms a reference value for the phase difference between the first signal (S1) and the third signal (S3) by calculating the difference between the counts of the two counters, and the second signal (S2) is an auxiliary signal generated by a delay stage (15, 16) and has a frequency that is substantially equal to the frequency of the first signal (S1) and the third signal (S3).

Claim 3

A phase comparator as claimed in claim 1, characterized in that the delay stage includes AND gate circuit means (15) and delay stage circuit means (16), responsive the signals at the two outputs of the first and second flip-flops (11, 12), for providing the second signal (S2).

Claim 4

A phase comparator as claimed in claim 1, characterized in that the evaluation unit (17) averages a series of phase differences between the first Signal (S1) and the third signal (S3).

Claim 5

A phase comparator as claimed in claim 1, characterized in that the evaluation unit (17) averages a series of phase differences.

Claim 6

A phase-locked loop with a digital phase comparator (10) comprising: a first flip-flop (11) which is settable by a given phase transition of a first signal (S1) and resettable by a given phase transition of a second signal (S2), and a first counter (13) which is enabled by the flip-flop (11) as long as the latter is set, and whose clock input (ck) is supplied with a clock signal (T) whose frequency is high compared with the frequencies of the first signal (S1) and the second signal (S2), characterized in that a second flip-flop (12) is provided which is settable by a given phase transition of a third signal (S3) and is resettable together with the first flip-flop (11) using the signal (S2), a second counter (14) is provided which is enabled by the second flip-flop (12) as long as the latter is set, and whose clock input (ck) is supplied with the clock signal (T), an evaluation unit (17) is provided which forms a reference value for the phase difference between the first signal (S1) and the third signal (S3) by calculating the difference between the counts of the two counters, and the second signal (S2) is an auxiliary signal generated by a delay stage (15, 16) and has a frequency that is substantially equal to the frequency of the first signal (S1) and the third signal (S3).

Claim 7

A phase-locked loop with a digital phase comparator (10) comprising: a first flip-flop (11) which is settable by a given phase transition of a first signal (S1) and resettable by a given phase transition of a second signal (S2), and a first counter (13) which is enabled by the flip-flop (11) as long as the latter is set, and whose clock input (ck) is supplied with a clock signal (T) whose frequency is high compared with the frequencies of the first signal (S1) and the second signal (S2), characterized in that a second flip-flop (12) is provided which is settable by a given phase transition of a third signal (S3) and is resettable together with the first flip-flop (11) using the signal (S2), a second counter (14) is provided which is enabled by the second flip-flop (12) as long as the latter is set, and whose clock input (ck) is supplied with the clock signal (T), an evaluation unit (17) is provided which forms a reference value for the phase difference between the first signal (S1) and the third signal (S3) by calculating the difference between the counts of the two counters, and the second signal (S2) is an auxiliary signal generated by a delay stage (15, 16) and has a frequency that is substantially equal to the frequency of the first signal (S1) and the third signal (S3).

Claim 8

A digital phase comparator (10), comprising: first flip flop means (11), responsive to clock setting signals (S1) having first phase transitions, responsive to a first logical "1" data signal, and further responsive to resetting signals (S2) having second phase transitions, for providing first counter enable signals (Q11); second flip flop means (12), responsive to clock setting signals (S3) having third phase transitions, responsive to a second logical "1" data signal, and further responsive to the resetting signals (S2), for providing second counter enable signals (Q12); delay stage means (15, 16), responsive to the first counter enable signals (Q11), and further responsive to the second counter enable signals (Q12), for providing the resetting signals (S2); first counter means (13), responsive to the first counter enable signals (Q11), and further responsive to time pulse clock signals (T), for providing first counter output signals; second counter means (14), responsive to the second counter enable signals (Q12), and further responsive to the time pulse clock signals (T), for providing second counter output signals; evaluation circuit means (17), responsive to the first counter output signals, and further responsive to the second counter output signals, for providing reference value signal depending on the phase difference between the first clock setting signals (S1) and the third clock setting signals (S3).

Claim 9

A digital phase comparator (10), comprising: first flip flop means (11), responsive to clock setting signals (S1) having first phase transitions, responsive to a first logical "1" data signal, and further responsive to resetting signals (S2) having second phase transitions, for providing first counter enable signals (Q11); second flip flop means (12), responsive to clock setting signals (S3) having third phase transitions, responsive to a second logical "1" data signal, and further responsive to the resetting signals (S2), for providing second counter enable signals (Q12); delay stage means (15, 16), responsive to the first counter enable signals (Q11), and further responsive to the second counter enable signals (Q12), for providing the resetting signals (S2); first counter means (13), responsive to the first counter enable signals (Q11), and further responsive to time pulse clock signals (T), for providing first counter output signals; second counter means (14), responsive to the second counter enable signals (Q12), and further responsive to the time pulse clock signals (T), for providing second counter output signals; evaluation circuit means (17), responsive to the first counter output signals, and further responsive to the second counter output signals, for providing reference value signal depending on the phase difference between the first clock setting signals (S1) and the third clock setting signals (S3).

Claim 10

A digital phase comparator (10) according to claim 6, wherein the delay stage means (16) includes an AND gate (15), responsive to the first counter enable signals (Q11), and further responsive to the second counter enable signals (Q12), for providing combined first and second counter enable signals (Q12).

Claim 11

A digital phase comparator (10) according to claim 7, wherein the delay stage means (16) also includes delay means (16), responsive to the combined first and second counter enable signals (Q12), for providing the resetting signals (S2).