Programmable controller having a means to accept a plurality of I/O devices mountable in arbitrary slots

Claim 2

A programmable controller, comprising: a central processing unit (CPU) for generating data and commands; a controlled unit coupled to the CPU and said controlled unit comprised of, a plurality of slots into which a plurality of input and output (I/O) devices are mounted; a plurality of I/O devices mounted in the slots; data bus whose bit lines being connected to the plurality of I/O devices in one-to-one correspondence basis, each bit line of the data bus representing I/O position data indicating into which slot the I/O device is mounted; each of the plurality of I/O devices including: means for generating an interrupt request signal for interrupting the CPU; I/O device position detector means for detecting that I/O device position indicating into which slot the I/O device is mounted and for generating the I/O device position data representing the I/O device position and having a predetermined priority level, wherein the priority levels of the I/O device position data for the plurality of I/O devices is different from each other; and means for transferring the I/O device position data from the I/O device position detector means through the corresponding bit of the data bus; means for latching simultaneously the I/O device position data transferred by the transfer means; means for determining the I/O device having the highest priority level using the I/O device position data latched by the latch means; and means for informing the CPU of the I/O device having the highest priority determined by the determining means.

Claim 3

A programmable controller, comprising: a central processing unit (CPU) for generating data and commands; a controlled unit coupled to the CPU and including: a plurality of slots into which a plurality of input and output (I/O) devices are mounted; a plurality of I/O devices mounted in the slots; data bus whose bit lines being connected to the plurality of I/O devices in one-to-one correspondence basis, each bit line of the data bus representing I/O position data indicating into which slot the I/O device is mounted; each of the plurality of I/O devices comprised of, means for generating an interrupt request signal for interrupting the CPU; I/O device position detector means for detecting that I/O device position indicating into which slot the I/O device is mounted and for generating the I/O device position data representing the I/O device position and having a predetermined priority level, wherein the priority levels of the I/O device position data for the plurality of I/O devices is different from each other; and means for transferring the I/O device position data from the I/O device position detector means through the corresponding bit of the data bus; means for latching simultaneously the I/O device position data transferred by the transfer means; means for setting arbitrary interrupt level with respect to the I/O devices; means for determining the I/O device having the highest priority level set by the setting means; and means for informing the CPU of the I/O device having the highest priority determined by the determining means.

Claim 4

A programmable controller, comprising: a central processing unit (CPU) for generating data and commands; a controlled unit coupled to the CPU and including: a plurality of slots into which a plurality of input and output (I/O) devices are mounted; a plurality of I/O devices mounted in the slots; data bus whose bit lines being connected to the plurality of I/O devices in one-to-one correspondence basis, each bit line of the data bus representing I/O position data indicating into which slot the I/O device is mounted; each of the plurality of I/O devices comprised of, means for generating an interrupt request signal for interrupting the CPU; I/O device position detector means for detecting that I/O device position indicating into which slot the I/O device is mounted and for generating the I/O device position data representing the I/O device position and having a predetermined priority level, wherein the priority levels of the I/O device position data for the plurality of I/O devices is different from each other; and means for transferring the I/O device position data from the I/O device position detector means through the corresponding bit of the data bus; means for latching simultaneously the I/O device position data transferred by the transfer means; means for setting arbitrary interrupt level with respect to the I/O devices; means for determining the I/O device having the highest priority level set by the setting means; and means for informing the CPU of the I/O device having the highest priority determined by the determining means.

Claim 5

A programmable controller, comprising: a central processing unit (CPU) for generating data and commands; a plurality of controlled units coupled to the CPU, each including: a plurality of slots into which a plurality of input and output (I/O) devices are mounted; a plurality of I/O devices mounted in the slots; data bus whose bit lines being connected to the plurality of I/O devices in one-to-one correspondence basis, each bit line of the data bus representing I/O position data indicating into which slot the I/O device is mounted; each of the plurality of I/O devices comprised of, means for generating an interrupt request signal for interrupting the CPU; I/O device position detector means for detecting that I/O device position indicating into which slot the I/O device is mounted and for generating the I/O device position data representing the I/O device position and having a predetermined priority level, wherein the priority levels of the I/O device position data for the plurality of I/O devices is different from each other; and means for transferring the I/O device position data from the I/O device position detector means through the corresponding bit of the data bus; means for latching simultaneously the I/O device position data transferred by the transfer means; means for setting arbitrary interrupt level with respect to the I/O devices; means for determining the I/O device having the highest priority level set by the setting means; means for generating unit identification data for identifying the control unit interrupting the CPU; and means for transferring the unit identification data to inform the CPU of the controlled unit interrupting thereto and data indicating the I/O device within the controlled unit and having the highest priority determined by the determining means.

Claim 6

A programmable controller, comprising: a central processing unit (CPU) for generating data and commands; a plurality of controlled units coupled to the CPU, each including: a plurality of slots into which a plurality of input and output (I/O) devices are mounted; a plurality of I/O devices mounted in the slots; data bus whose bit lines being connected to the plurality of I/O devices in one-to-one correspondence basis, each bit line of the data bus representing I/O position data indicating into which slot the I/O device is mounted; each of the plurality of I/O devices comprised of, means for generating an interrupt request signal for interrupting the CPU; I/O device position detector means for detecting that I/O device position indicating into which slot the I/O device is mounted and for generating the I/O device position data representing the I/O device position and having a predetermined priority level, wherein the priority levels of the I/O device position data for the plurality of I/O devices is different from each other; and means for transferring the I/O device position data from the I/O device position detector means through the corresponding bit of the data bus; means for latching simultaneously the I/O device position data transferred by the transfer means; means for setting arbitrary interrupt level with respect to the I/O devices; means for determining the I/O device having the highest priority level set by the setting means; means for generating unit identification data for identifying the control unit interrupting the CPU; and means for transferring the unit identification data to inform the CPU of the controlled unit interrupting thereto and data indicating the I/O device within the controlled unit and having the highest priority determined by the determining means.