Expandable repeater

Claim 2

A computer network including a plurality of repeaters, at least one of the plurality of repeaters comprising: a plurality of repeater circuits, each repeater circuit having a plurality of ports for receiving data at one port and transmitting said data to a number of other ports; means, coupled to said plurality of repeater circuits, for relaying said data from one of said plurality of repeater circuits to other of said plurality of repeater circuits for transmission of said data from said other repeater circuits' said number of other ports; identifying means, coupled to each of the plurality of repeater circuits, for identifying a predefined activity among said plurality of ports of said plurality of repeater circuits; and means, coupled to said identifying means, for coordinating synchronized concurrent processing of said predefined activity by said plurality of repeater circuits so that said plurality of repeater circuits function as a single repeater.

Claim 3

The computer network of claim 1 in which within said at least one repeater said predefined activity comprises a collision.

Claim 4

The computer network of claim 2 wherein each said repeater circuit includes means for processing said collision among its said plurality of ports.

Claim 5

The computer network of claim 3 in which said at least one repeater further comprises: means, coupled to said each processing means, for distributing said collision processing among said plurality of repeater circuits to have the repeater process said collision as a single unit.

Claim 6

The computer network of claim 1 wherein each said repeater circuit includes means for processing said predefined activity among its said plurality of ports.

Claim 7

The computer network of claim 5 in which said at least one repeater further comprises: means, coupled to each said processing means, for distributing said predefined activity processing among said plurality of repeater circuits to have the repeater process said predefined activity as a single unit.

Claim 8

The computer network of claim 1 wherein all of said plurality of ports include said predefined activity to be identified.

Claim 9

A computer network including a plurality of repeaters, at least one of the repeaters comprising: a first and a second repeater circuit each having a predetermined number of ports for receipt and transmission of data, each said repeater circuit implementing a sequence of steps to receive data at one port, repeat said data from a number of other ports, and means for processing collisions; an expansion port, coupled to said first and second repeater circuit, for relaying particular data received at a port of a particular repeater circuit to another repeater circuit; and an arbiter function, coupled to said expansion port of each said repeater circuit, for implementing a protocol causing said first and second repeater circuits to function as a single repeater by coordinating concurrent processing of data and collision information by said first and second repeater circuits.

Claim 10

A computer network including a plurality of repeaters, at least one of the repeaters comprising: a first and a second repeater circuit each having a predetermined number of ports for receipt and transmission of data, each said repeater circuit implementing a sequence of steps to receive data at one port, repeat said data from a number of other ports, and means for processing collisions; an expansion port, coupled to said first and second repeater circuit, for relaying particular data received at a port of a particular repeater circuit to another repeater circuit; and an arbiter function, coupled to said expansion port of each said repeater circuit, for implementing a protocol causing said first and second repeater circuits to function as a single repeater by coordinating concurrent processing of data and collision information by said first and second repeater circuits.

Claim 11

A computer network including a plurality of repeaters, at least one repeater comprising: a plurality of repeater circuits each having a predetermined number of ports for receipt and transmission of data and including a state machine function supporting a set of predefined repeater functions; and means, coupled to said plurality of repeater circuits, for coordinating implementation of each repeater's set of predefined repeater functions by synchronizing each said state machine function to implement said set of predefined repeater functions for a combination of said plurality of repeater circuits to operate said combination of said plurality of repeater circuits as a single repeater implementing said set of predefined repeater functions.

Claim 12

A computer network including a plurality of repeaters, at least one repeater comprising: a plurality of repeater circuits each having a predetermined number of ports for receipt and transmission of data and including a state machine function supporting a set of predefined repeater functions; and means, coupled to said plurality of repeater circuits, for coordinating implementation of each repeater's set of predefined repeater functions by synchronizing each said state machine function to implement said set of predefined repeater functions for a combination of said plurality of repeater circuits to operate said combination of said plurality of repeater circuits as a single repeater implementing said set of predefined repeater functions.

Claim 13

The computer network of claim 9 wherein said plurality of repeater circuits comprises more than three repeater circuits.

Claim 14

The computer network of claim 9 wherein all of said plurality of repeater circuits are coordinated.

Claim 15

A computer network including a plurality of repeaters, at least one of the plurality of repeaters, comprising: a plurality of repeater circuits, each having a predetermined number of ports for receipt and transmission of data and including a state machine for implementing a set of predefined repeater functions including processing of collisions among its ports, each said repeater circuit comprising: means for asserting an output signal when one of its ports has received a data group; means for providing said data group to a first bidirectional channel in response to assertion of a first input signal if said repeater circuit has asserted said output signal, otherwise said repeater circuit transmitting from its ports data provided on said first bidirectional channel in response to assertion of said first input signal; means for detecting a first collision type or a second collision type and initiating an appropriate collision processing sequence, said repeater circuit asserting a signal on a second bidirectional channel in response to concurrent assertion of said output signal and said first input signal, said repeater circuit additionally asserting a signal on said first bidirectional line if said collision is of said first collision type and deasserting said signal on said first bidrectional line if said collision is of said second collision type; means for responding to an assertion of said first input signal and a concurrent assertion of said signal on said second bidirectional channel to initiate collision processing for said first collision type if said signal on said first bidirectional channel has been asserted, otherwise initiating second collision type processing if said signal on said first bidirectional channel has been deasserted; means for initiating collision processing upon assertion of a second input signal; an arbiter function, coupled to said plurality of repeater circuits, for asserting said first input signal to all repeater circuits if only one output signal is asserted, otherwise said arbiter function asserting said second input signal; and an expansion bus, providing said output signals of each repeater circuit to said arbiter function, providing said first input signal from said arbiter function to all said repeater circuits in parallel, providing said second input signal from said arbiter function to all said repeater circuits in parallel, said expansion bus intercoupling said first bidirectional channels of said plurality of repeater circuits to each another in parallel and intercoupling said second bidirectional channels of said plurality of repeater circuits to each other in parallel.

Claim 16

A computer network including a plurality of repeaters, at least one of the plurality of repeaters, comprising: a plurality of repeater circuits, each having a predetermined number of ports for receipt and transmission of data and including a state machine for implementing a set of predefined repeater functions including processing of collisions among its ports, each said repeater circuit comprising: means for asserting an output signal when one of its ports has received a data group; means for providing said data group to a first bidirectional channel in response to assertion of a first input signal if said repeater circuit has asserted said output signal, otherwise said repeater circuit transmitting from its ports data provided on said first bidirectional channel in response to assertion of said first input signal; means for detecting a first collision type or a second collision type and initiating an appropriate collision processing sequence, said repeater circuit asserting a signal on a second bidirectional channel in response to concurrent assertion of said output signal and said first input signal, said repeater circuit additionally asserting a signal on said first bidirectional line if said collision is of said first collision type and deasserting said signal on said first bidrectional line if said collision is of said second collision type; means for responding to an assertion of said first input signal and a concurrent assertion of said signal on said second bidirectional channel to initiate collision processing for said first collision type if said signal on said first bidirectional channel has been asserted, otherwise initiating second collision type processing if said signal on said first bidirectional channel has been deasserted; means for initiating collision processing upon assertion of a second input signal; an arbiter function, coupled to said plurality of repeater circuits, for asserting said first input signal to all repeater circuits if only one output signal is asserted, otherwise said arbiter function asserting said second input signal; and an expansion bus, providing said output signals of each repeater circuit to said arbiter function, providing said first input signal from said arbiter function to all said repeater circuits in parallel, providing said second input signal from said arbiter function to all said repeater circuits in parallel, said expansion bus intercoupling said first bidirectional channels of said plurality of repeater circuits to each another in parallel and intercoupling said second bidirectional channels of said plurality of repeater circuits to each other in parallel.

Claim 17

A computer network which includes an expansion method for a repeater circuit having a limited port number with an expansion capability, the method comprising the steps of: providing the first repeater circuit in a discrete chip having a preestablished number of ports, said repeater circuit including an expansion bus for conveying a status of state machine functions to other repeater circuits coupled on said expansion bus; coupling a second repeater circuit also having a preestablished number of ports and an expansion port to said expansion port of the repeater circuit; and synchronizing said state machine functions of said second repeater circuit and the first repeater circuit using said expansion bus to provide a single repeater from said repeater circuits.

Claim 18

A computer network which includes an expansion method for a repeater circuit having a limited port number with an expansion capability, the method comprising the steps of: providing the first repeater circuit in a discrete chip having a preestablished number of ports, said repeater circuit including an expansion bus for conveying a status of state machine functions to other repeater circuits coupled on said expansion bus; coupling a second repeater circuit also having a preestablished number of ports and an expansion port to said expansion port of the repeater circuit; and synchronizing said state machine functions of said second repeater circuit and the first repeater circuit using said expansion bus to provide a single repeater from said repeater circuits.