Interface between a register file which arbitrates between a number of single cycle and multiple cycle functional units

Claim 2

A microprocessor comprising: an instruction decoder (8); a register file (6); a plurality of first functional units for independently executing a plurality of first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; a microinstruction bus (112) connected to said instruction decoder, said register file, and to each of said first and second functional units; an interface; said instruction decoder being connected to said interface; a return bus (110) connected to said register file (6); a cancellation line (102) connected between said register file and each one of said first and second functional units; said register file including means for asserting said cancellation line upon a condition that a current microinstruction on said microinstruction bus (112) is valid; means in said register file for disasserting said cancellation line upon a condition that any one register in said register file is busy; a single cycle line connected from at least one of said single cycle functional units to said multiple cycle functional units; said multiple cycle functional units and said single cycle functional units being connected to said interface and to said return bus; said single cycle line being asserted by one of said single cycle functional units upon a condition that said single cycle functional unit requests access to said return bus; and, arbitration means connected to said single cycle line and to said cancellation line for preventing access to said return bus upon a condition that said single cycle line and said cancellation line are asserted.

Claim 3

The microprocessor in accordance with claim 1 further comprising: arbitration means for arbitrating requests by each of said multiple cycle functional units; said arbitration means including means for granting a request upon a condition that said single cycle line is not asserted; and, means connected to said arbitration means for returning data and a register specifier to said register file in response to said arbitration means granting said request.

Claim 4

The microprocessor in accordance with claim 1 further comprising: arbitration means for arbitrating requests by each of said multiple cycle functional units; said arbitration means including means for granting a request upon a condition that said single cycle line is asserted and said single cycle line is not asserted; and, means connected to said arbitration means for returning data and a register specifier to said register file in response to said arbitration means granting said request.

Claim 5

In a pipelined microprocessor which includes an instruction decoder (8), a REG interface (23), a MEM interface (33), a register file (6) of registers including destination registers, a plurality of first functional units for independently executing first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; and, a microinstruction bus (112) connected to said instruction decoder, said register file, and to each of said first and second functional units; a single cycle line (102) connected from at least one of said single cycle functional units to said multiple cycle functional units; a method comprising the steps of: (A) connecting a Scbok line (102) between said instruction decoder, said register file and to each one of said first and second functional units; (B) asserting said Scbok line upon a condition that a current microinstruction on said microinstruction bus (112) is valid; (C) disasserting said Scbok signal upon a condition that any one register in said register file needed by said current instruction on said microinstruction bus is busy; (D) asserting said single cycle line (102) upon a condition that said single cycle functional unit requests access to said destination bus; and, (E) preventing access to said destination bus upon a condition that said single cycle line and said ScbOk line are asserted.

Claim 6

In a pipelined microprocessor which includes an instruction decoder (8), a REG interface (23), a MEM interface (33), a register file (6) of registers including destination registers, a plurality of first functional units for independently executing first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; and, a microinstruction bus (112) connected to said instruction decoder, said register file, and to each of said first and second functional units; a single cycle line (102) connected from at least one of said single cycle functional units to said multiple cycle functional units; a method comprising the steps of: (A) connecting a Scbok line (102) between said instruction decoder, said register file and to each one of said first and second functional units; (B) asserting said Scbok line upon a condition that a current microinstruction on said microinstruction bus (112) is valid; (C) disasserting said Scbok signal upon a condition that any one register in said register file needed by said current instruction on said microinstruction bus is busy; (D) asserting said single cycle line (102) upon a condition that said single cycle functional unit requests access to said destination bus; and, (E) preventing access to said destination bus upon a condition that said single cycle line and said ScbOk line are asserted.

Claim 7

The method in accordance with claim 4 comprising the further steps of: (F) (G) arbitrating requests by each of said multiple cycle functional units; (G) (H) granting a request upon a condition that said single cycle line is not asserted; and, (H) (I) returning data and a register specifier to said register file in response to said arbitrating means granting said request.

Claim 8

The method in accordance with claim 4 comprising the further steps of: (G) arbitrating requests by each of said multiple cycle functional units; (H) granting a request upon the condition that said single cycle line is asserted and said scbok line is not asserted; and, (H) returning data and a register specifier to said register file in response to said arbitrating means granting said request.

Claim 9

A microprocessor comprising: an instruction decoder (8); a register file (6); a plurality of first functional units for independently executing a plurality of first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution; a microinstruction bus (112) connected to said instruction decoder, said register file, and to each of said first and second functional units; a REG interface; said instruction decoder being connected to said REG interface; a destination bus (110) connected to said register file (6); a Scbok line (102) connected between said instruction decoder, said register file and to each one of said first and second functional units; said instruction decoder including first logic for asserting said Scbok line upon a condition that a current microinstruction on said microinstruction bus (112) is valid; a second logic in said register file for disasserting said Scbok signal upon a condition that any one register in said register file needed by an instruction on said microinstruction bus is busy; a single cycle line (102) connected from at least one of said single cycle functional units to said multiple cycle functional units; said single cycle line being asserted by one of said single cycle functional units upon a condition that said single cycle functional unit requests access to said destination bus; said multiple cycle functional units and single cycle functional units being connected to said REG interface and to said destination bus; and, an arbitration logic connected to said single cycle line and to said ScbOk line for preventing access to said destination bus upon a condition that said single cycle line and said ScbOk line are asserted.

Claim 10

A microprocessor comprising: an instruction decoder (8); a register file (6); a plurality of first functional units for independently executing a plurality of first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution; a microinstruction bus (112) connected to said instruction decoder, said register file, and to each of said first and second functional units; a REG interface; said instruction decoder being connected to said REG interface; a destination bus (110) connected to said register file (6); a Scbok line (102) connected between said instruction decoder, said register file and to each one of said first and second functional units; said instruction decoder including first logic for asserting said Scbok line upon a condition that a current microinstruction on said microinstruction bus (112) is valid; a second logic in said register file for disasserting said Scbok signal upon a condition that any one register in said register file needed by an instruction on said microinstruction bus is busy; a single cycle line (102) connected from at least one of said single cycle functional units to said multiple cycle functional units; said single cycle line being asserted by one of said single cycle functional units upon a condition that said single cycle functional unit requests access to said destination bus; said multiple cycle functional units and single cycle functional units being connected to said REG interface and to said destination bus; and, an arbitration logic connected to said single cycle line and to said ScbOk line for preventing access to said destination bus upon a condition that said single cycle line and said ScbOk line are asserted.

Claim 11

In a data processor connected to a main memory and a microinstruction bus for carrying a current microinstruction including an opcode field, said data processor including single cycle coprocessors and multi-cycle processors; an instruction decoder; a register file comprised of a plurality of registers; said register file including busy bits associated with each register in said register file; a cancellation line connected to said register file and to first ones of said single cycle coprocessors and multi-cycle processors, said cancellation line when driven to a first state, indicating that a first particular register of said plurality of registers or a single cycle coprocessor or a multi-cycle processor used by a current register type of microinstruction on said microinstruction bus is available for a register execution operation and, when driven to a second state, indicating that said first particular register or said single cycle coprocessor or said multi-cycle processor used by said current register type of microinstruction on said microinstruction bus is not available for a register execution operation; said cancellation line being initially driven to said first state; first means connected to said register file for checking said first particular register needed to execute said microinstruction to determine if said first particular register is busy; second means connected to said microinstruction bus for checking said opcode field of said microinstruction to determine if said microinstruction is a single cycle microinstruction, third means connected to said first means, said second means, and to said cancellation line, for driving said cancellation line to said second state upon a condition that said microinstruction is a single cycle microinstruction and that said first particular register needed by said single cycle microinstruction is busy; a return bus connected to said register file; a single cycle line connected from at one of said single cycle processors to said multiple cycle processors; said single cycle line being asserted by one of said single cycle processors upon a condition that said one of said single cycle processors requests access to said return bus; said multiple cycle processors and single cycle processors being connected to said interface and to said return bus; and, arbitration means connected to said single cycle line and to said cancellation line for preventing access to said return bus upon a condition that said single cycle line and said cancellation line are asserted.

Claim 12

In a data processor connected to a main memory and a microinstruction bus for carrying a current microinstruction including an opcode field, said data processor including single cycle coprocessors and multi-cycle processors; an instruction decoder; a register file comprised of a plurality of registers; said register file including busy bits associated with each register in said register file; a cancellation line connected to said register file and to first ones of said single cycle coprocessors and multi-cycle processors, said cancellation line when driven to a first state, indicating that a first particular register of said plurality of registers or a single cycle coprocessor or a multi-cycle processor used by a current register type of microinstruction on said microinstruction bus is available for a register execution operation and, when driven to a second state, indicating that said first particular register or said single cycle coprocessor or said multi-cycle processor used by said current register type of microinstruction on said microinstruction bus is not available for a register execution operation; said cancellation line being initially driven to said first state; first means connected to said register file for checking said first particular register needed to execute said microinstruction to determine if said first particular register is busy; second means connected to said microinstruction bus for checking said opcode field of said microinstruction to determine if said microinstruction is a single cycle microinstruction, third means connected to said first means, said second means, and to said cancellation line, for driving said cancellation line to said second state upon a condition that said microinstruction is a single cycle microinstruction and that said first particular register needed by said single cycle microinstruction is busy; a return bus connected to said register file; a single cycle line connected from at one of said single cycle processors to said multiple cycle processors; said single cycle line being asserted by one of said single cycle processors upon a condition that said one of said single cycle processors requests access to said return bus; said multiple cycle processors and single cycle processors being connected to said interface and to said return bus; and, arbitration means connected to said single cycle line and to said cancellation line for preventing access to said return bus upon a condition that said single cycle line and said cancellation line are asserted.

Claim 13

The microprocessor in accordance with claim 8 wherein said arbitration means includes means for granting a request upon a condition that said single cycle line is not asserted; and, means for returning data and a register specifier to said register file said condition that said single cycle line is not asserted.

Claim 14

A data processor connected to a main memory and a microinstruction bus for carrying a current microinstruction, said current microinstruction including source operands, said data processor including a register file comprised of a plurality of registers including destination registers; said register file including busy bits associated with each register in said register file; an instruction decoder; a REG interface; a MEM interface; a plurality of first processors for independently executing first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second processors for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; a microinstruction bus connected to said instruction decoder, said register file, and to each of said first and second processors; a cancellation line connected between said instruction decoder, said register file and to each one of said first and second processors; a single cycle line connected from at least one of said single cycle processors to said multiple cycle processors; a method comprising the steps of: (A) driving said cancellation line to a first state to signal that said current microinstruction on said microinstruction bus is valid; (B) driving information from said register file on a machine bus during a first phase of a first clock cycle; (C) reading said source operands of said current microinstruction during a second phase of said first clock cycle; (D) checking said busy bits of all registers needed by said source operands to execute said current microinstruction register file; (E) driving said cancellation line to a second state during said second phase of said first clock cycle upon a condition that any one of said registers needed by said microinstruction is marked busy or a single cycle coprocessor or a multi-cycle processor used by a current register type of microinstruction on said microinstruction bus is unavailable for a register execution operation; (F) reissuing said current microinstruction during a clock cycle subsequent to said first clock cycle upon a condition that said cancellation line is driven to said second state; (G) asserting said cancellation line to signal that a current microinstruction on said microinstruction bus is valid; (H) disasserting said cancellation signal upon a condition that any one register in said register file needed by the instruction on said microinstruction bus is busy; (I) asserting said single cycle line upon a condition that one of said second processors requests access to said destination bus; and, (J) preventing access to said destination bus upon a condition that said single cycle line and said cancellation line are asserted.

Claim 15

A data processor connected to a main memory and a microinstruction bus for carrying a current microinstruction, said current microinstruction including source operands, said data processor including a register file comprised of a plurality of registers including destination registers; said register file including busy bits associated with each register in said register file; an instruction decoder; a REG interface; a MEM interface; a plurality of first processors for independently executing first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second processors for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; a microinstruction bus connected to said instruction decoder, said register file, and to each of said first and second processors; a cancellation line connected between said instruction decoder, said register file and to each one of said first and second processors; a single cycle line connected from at least one of said single cycle processors to said multiple cycle processors; a method comprising the steps of: (A) driving said cancellation line to a first state to signal that said current microinstruction on said microinstruction bus is valid; (B) driving information from said register file on a machine bus during a first phase of a first clock cycle; (C) reading said source operands of said current microinstruction during a second phase of said first clock cycle; (D) checking said busy bits of all registers needed by said source operands to execute said current microinstruction register file; (E) driving said cancellation line to a second state during said second phase of said first clock cycle upon a condition that any one of said registers needed by said microinstruction is marked busy or a single cycle coprocessor or a multi-cycle processor used by a current register type of microinstruction on said microinstruction bus is unavailable for a register execution operation; (F) reissuing said current microinstruction during a clock cycle subsequent to said first clock cycle upon a condition that said cancellation line is driven to said second state; (G) asserting said cancellation line to signal that a current microinstruction on said microinstruction bus is valid; (H) disasserting said cancellation signal upon a condition that any one register in said register file needed by the instruction on said microinstruction bus is busy; (I) asserting said single cycle line upon a condition that one of said second processors requests access to said destination bus; and, (J) preventing access to said destination bus upon a condition that said single cycle line and said cancellation line are asserted.

Claim 16

The method in accordance with claim 10 comprising the further steps of: (K) arbitrating requests by each of said second processors upon a condition that said single cycle line is not asserted; and, (L) returning data and a register specifier to said register file.

Claim 17

A data processor connected to a main memory and a microinstruction bus for carrying a current microinstruction, said current microinstruction including an opcode field, said data processor including: a register file comprised of a plurality of registers; said register file including scoreboard bits associated with each of said plurality of registers in said register file, In a pipelined microprocessor which includes an instruction decoder; a REG interface; a MEM interface; said register file including destination registers; a plurality of first functional units for independently executing first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; and, a microinstruction bus connected to said instruction decoder, said register file, and to each of said first and second functional units; a single cycle line connected from at least one of said single cycle functional units to said multiple cycle functional units; a Scbok line connected between said instruction decoder, said register file and to each one of said first and second functional units; a method comprising the steps of: A. driving said Scbok line to a first state to indicate that a register or a single cycle or multi-cycle coprocessor used by a current register type of microinstruction on said microinstruction bus is available for a register execution operation; B. checking said busy bits of all registers needed to execute said microinstruction to determine if they are all available; C. checking said opcode field of said microinstruction to determine if said microinstruction is a single cycle microinstruction or a multi-cycle microinstruction, D. driving said Scbok line to a second state upon a condition that said microinstruction is a single cycle and that a register or a single cycle coprocessor or a multi-cycle processor needed by said microinstruction is busy; (E) asserting said Scbok line to signal that a current microinstruction on said microinstruction bus is valid; (F) disasserting said Scbok signal upon a condition that any one register in said register file needed by the instruction on said microinstruction bus is busy; (G) asserting said single cycle line upon a condition that said single cycle functional unit requests access to said destination bus; and, (H) preventing access to said destination bus upon a condition that said single cycle line and said ScbOk line are asserted.

Claim 18

A data processor connected to a main memory and a microinstruction bus for carrying a current microinstruction, said current microinstruction including an opcode field, said data processor including: a register file comprised of a plurality of registers; said register file including scoreboard bits associated with each of said plurality of registers in said register file, In a pipelined microprocessor which includes an instruction decoder; a REG interface; a MEM interface; said register file including destination registers; a plurality of first functional units for independently executing first microinstructions that take a plurality of clock cycles to complete execution, said first microinstructions being issued by said instruction decoder; a plurality of second functional units for independently executing second microinstructions that take a single clock cycle to complete execution, said second microinstructions being issued by said instruction decoder; and, a microinstruction bus connected to said instruction decoder, said register file, and to each of said first and second functional units; a single cycle line connected from at least one of said single cycle functional units to said multiple cycle functional units; a Scbok line connected between said instruction decoder, said register file and to each one of said first and second functional units; a method comprising the steps of: A. driving said Scbok line to a first state to indicate that a register or a single cycle or multi-cycle coprocessor used by a current register type of microinstruction on said microinstruction bus is available for a register execution operation; B. checking said busy bits of all registers needed to execute said microinstruction to determine if they are all available; C. checking said opcode field of said microinstruction to determine if said microinstruction is a single cycle microinstruction or a multi-cycle microinstruction, D. driving said Scbok line to a second state upon a condition that said microinstruction is a single cycle and that a register or a single cycle coprocessor or a multi-cycle processor needed by said microinstruction is busy; (E) asserting said Scbok line to signal that a current microinstruction on said microinstruction bus is valid; (F) disasserting said Scbok signal upon a condition that any one register in said register file needed by the instruction on said microinstruction bus is busy; (G) asserting said single cycle line upon a condition that said single cycle functional unit requests access to said destination bus; and, (H) preventing access to said destination bus upon a condition that said single cycle line and said ScbOk line are asserted.

Claim 19

The method in accordance with claim 12 comprising the further steps of: (I) arbitrating requests by each of said multiple cycle functional units upon a condition that said single cycle line is not asserted; and, (J) returning data and a register specifier to said register file.