Edge crossing circuitry for SIMD architecture

Claim 1

A parallel processor comprising: four or more processing units; edge crossing circuitry for receiving an item of data that includes two or more bits and for bit serially providing the item of data; the edge crossing circuitry comprising an edge crossing shift register; interconnecting circuitry for interconnecting a set of at least two of the processing units and the edge crossing circuitry; each processing unit in the set of at least two of the processing units comprising an internal shift register; the interconnecting circuitry interconnecting pairs of the processing units in the set to form an array of processing units that includes all the processing units in the set, the array including a first edge processing unit that is in the set and is at a first edge of the array; the interconnecting circuitry interconnecting the internal shift register of each processing unit in each pair of processing units to the internal shift register of the other processing unit in the pair so that an item of data from the internal shift register of either of the processing units in the pair can be transferred to the internal shift register of the other processing unit in the pair; the interconnecting circuitry further connecting the edge crossing circuitry and the first edge processing unit so that items of data from the edge crossing shift register can be transferred bit serially to the internal shift register of the first edge processing unit; the internal shift register of each of the processing units in the set and the edge crossing shift register together forming an extended shift register; data transfer circuitry connecting the array of processing units to the edge crossing circuitry so that the data transfer circuitry can transfer an item of data obtained from the array of processing units to the edge crossing circuitry; and control circuitry connected for providing control signals to the array of processing units, the data transfer circuitry, and the edge crossing circuitry; the control signals causing the data transfer circuitry to transfer a first item of data obtained from the array of processing units to the edge crossing circuitry, causing a shift of the extended shift register so that the edge crossing shift register provides a bit from the first item of data to the processing unit shift register of the first edge processing unit through the interconnecting circuitry, and causing the array of processing units to perform an operation; the first item of data relating to part of a first segment of an image, the image also including a second segment adjacent to the first segment; in performing the operation, one of the processing units using the bit from the first item of data to obtain a second item of data relating to a part of the second segment that is across an edge from the part of the first segment.