Semiconductor device and method of screening the same

Claim 2

A semiconductor device, comprising: a potential source having a first potential; first and second circuit blocks, said first circuit block connected to said potential source and applied with said first potential during both a stress test operation of said semiconductor device and a normal operation of said semiconductor device; and a potential boosting circuit coupled to said potential source and to said second circuit block, said potential boosting circuit responsive to a boosting circuit disable signal during one of the stress test operation and the normal operation for outputting said first potential to said second circuit block and responsive to a boosting circuit enable signal during the other of the stress test operation and the normal operation for outputting a second potential internally boosted from said first potential to said second circuit block; wherein said potential boosting circuit comprises: a first logic gate having a first input receiving said boosting circuit enable signal, a second input receiving said boosting circuit disable signal, and an output; a first inverter having an input connected to said output of said first logic gate, and an output; a voltage boosting capacitor having a first terminal connected to said output of said first inverter, and a second terminal; a first precharge transistor having a first terminal connected to said potential source, a second terminal connected to said second terminal of said voltage boosting capacitor, and a gate applied with a precharge signal; a flip-flop circuit connected to a node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor and a reference potential, said flip-flop having first and second inputs and first and second outputs; a second precharge transistor having a first terminal connected to said first output of said flip-flop, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a second inverter having an input connected to said second output of said flip-flop, and an output; a third precharge transistor having a first terminal connected to said output of said second inverter, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a second logic gate having at least one input receiving address data, a second input receiving said boosting circuit enable signal, a third input receiving said boosting circuit disable signal, and an output connected to said first input of said flip-flop; and a third inverter having an input connected to said output of said second logic gate and an output connected to said second input of said flip-flop.

Claim 3

A semiconductor device, comprising: a potential source having a first potential; first and second circuit blocks, said first circuit block connected to said potential source and applied with said first potential during both a stress test operation of said semiconductor device and a normal operation of said semiconductor device; and a potential boosting circuit coupled to said potential source and to said second circuit block, said potential boosting circuit responsive to a boosting circuit disable signal during one of the stress test operation and the normal operation for outputting said first potential to said second circuit block and responsive to a boosting circuit enable signal during the other of the stress test operation and the normal operation for outputting a second potential internally boosted from said first potential to said second circuit block; wherein said potential boosting circuit comprises: a first inverter having an input receiving said boosting circuit enable signal, and an output; a second inverter having an input connected to said output of said first inverter, and an output; a voltage boosting capacitor having a first terminal connected to said output of said second inverter, and a second terminal; a first precharge transistor having a first terminal connected to said potential source, a second terminal connected to said second terminal of said voltage boosting capacitor, and a gate applied with a precharge signal; a flip-flop circuit connected to a node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor and a reference potential, said flip-flop having first and second inputs and first and second outputs; a second precharge transistor having a first terminal connected to said first output of said flip-flop, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a third inverter having an input connected to said second output of said flip-flop, and an output; a third precharge transistor having a first terminal connected to said output of said third inverter, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a logic gate having at least one input receiving address data, a second input receiving said boosting circuit enable signal, and an output connected to said first input of said flip-flop; a fourth inverter having an input connected to said output of said logic gate and an output connected to said second input of said flip-flop; and a switching transistor having a first terminal connected to said potential source, a second terminal connected to said node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor, and a gate receiving said boosting circuit disable signal.

Claim 4

A semiconductor device, comprising: a potential source having a first potential; first and second circuit blocks, said first circuit block connected to said potential source and applied with said first potential during both a stress test operation of said semiconductor device and a normal operation of said semiconductor device; and a potential boosting circuit coupled to said potential source and to said second circuit block, said potential boosting circuit responsive to a boosting circuit disable signal during one of the stress test operation and the normal operation for outputting said first potential to said second circuit block and responsive to a boosting circuit enable signal during the other of the stress test operation and the normal operation for outputting a second potential internally boosted from said first potential to said second circuit block; wherein said potential boosting circuit comprises: a first inverter having an input receiving said boosting circuit enable signal, and an output; a second inverter having an input connected to said output of said first inverter, and an output; a voltage boosting capacitor having a first terminal connected to said output of said second inverter, and a second terminal; a first precharge transistor having a first terminal connected to said potential source, a second terminal connected to said second terminal of said voltage boosting capacitor, and a gate applied with a precharge signal; a flip-flop circuit connected to a node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor and a reference potential, said flip-flop having first and second inputs and first and second outputs; a second precharge transistor having a first terminal connected to said first output of said flip-flop, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a third inverter having an input connected to said second output of said flip-flop, and an output; a third precharge transistor having a first terminal connected to said output of said third inverter, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a logic gate having at least one input receiving address data, a second input receiving said boosting circuit enable signal, and an output connected to said first input of said flip-flop; a fourth inverter having an input connected to said output of said logic gate and an output connected to said second input of said flip-flop; and a switching transistor having a first terminal connected to said potential source, a second terminal connected to said node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor, and a gate receiving said boosting circuit disable signal.

Claim 5

A semiconductor device comprising: a potential source having a first potential; first and second circuit blocks, said first circuit block connected to said potential source and applied with said first potential during both a stress test operation of said semiconductor device and a normal operation of said semiconductor device; and a potential boosting circuit coupled to said potential source and to said second circuit block, said potential boosting circuit responsive to a boosting circuit disable signal during one of the stress test operation and the normal operation for outputting said first potential to said second circuit block and responsive to a boosting circuit enable signal during the other of the stress test operation and the normal operation for outputting a second potential internally boosted from said first potential to said second circuit block; wherein said potential boosting circuit comprises: a first inverter having an input receiving said boosting circuit enable signal, and an output; a second inverter having an input connected to said output of said first inverter, and an output; a voltage boosting capacitor having a first terminal connected to said output of said second inverter, and a second terminal; a first precharge transistor having a first terminal connected to said potential source, a second terminal connected to said second terminal of said voltage boosting capacitor, and a gate applied with a precharge signal; a flip-flop circuit connected to a node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor and a reference potential, said flip-flop having first and second inputs and first and second outputs; a second precharge transistor having a first terminal connected to said first output of said flip-flop, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a third inverter having an input connected to said second output of said flip-flop, and an output; a third precharge transistor having a first terminal connected to said output of said third inverter, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a logic gate having at least one input receiving address data, a second input receiving said boosting circuit enable signal, and an output connected to said first input of said flip-flop; a fourth inverter having an input connected to said output of said logic gate and an output connected to said second input of said flip-flop; and a switching transistor having a first terminal connected to a node between an output of said second inverter and said first terminal of said voltage boosting capacitor, a second terminal connected to said node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor, and a gate receiving said boosting circuit disable signal.

Claim 6

A semiconductor device comprising: a potential source having a first potential; first and second circuit blocks, said first circuit block connected to said potential source and applied with said first potential during both a stress test operation of said semiconductor device and a normal operation of said semiconductor device; and a potential boosting circuit coupled to said potential source and to said second circuit block, said potential boosting circuit responsive to a boosting circuit disable signal during one of the stress test operation and the normal operation for outputting said first potential to said second circuit block and responsive to a boosting circuit enable signal during the other of the stress test operation and the normal operation for outputting a second potential internally boosted from said first potential to said second circuit block; wherein said potential boosting circuit comprises: a first inverter having an input receiving said boosting circuit enable signal, and an output; a second inverter having an input connected to said output of said first inverter, and an output; a voltage boosting capacitor having a first terminal connected to said output of said second inverter, and a second terminal; a first precharge transistor having a first terminal connected to said potential source, a second terminal connected to said second terminal of said voltage boosting capacitor, and a gate applied with a precharge signal; a flip-flop circuit connected to a node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor and a reference potential, said flip-flop having first and second inputs and first and second outputs; a second precharge transistor having a first terminal connected to said first output of said flip-flop, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a third inverter having an input connected to said second output of said flip-flop, and an output; a third precharge transistor having a first terminal connected to said output of said third inverter, a second terminal connected to said reference potential, and a gate applied with said precharge signal; a logic gate having at least one input receiving address data, a second input receiving said boosting circuit enable signal, and an output connected to said first input of said flip-flop; a fourth inverter having an input connected to said output of said logic gate and an output connected to said second input of said flip-flop; and a switching transistor having a first terminal connected to a node between an output of said second inverter and said first terminal of said voltage boosting capacitor, a second terminal connected to said node between said second terminal of said voltage boosting capacitor and said second terminal of said first precharge transistor, and a gate receiving said boosting circuit disable signal.

Claim 7

A semiconductor device, comprising: a potential source having a first potential; an output buffer; a potential changing circuit coupled to said potential source and to said output buffer, said potential changing circuit responsive to a changing circuit control signal during one of a stress test operation and a normal operation for outputting said first potential to said output buffer and responsive to said changing circuit control signal during the other of the stress test operation and the normal operation for outputting a second potential different than said first potential to said output buffer; wherein said potential changing circuit comprises: a first MOS transistor of a first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving an input signal; a second MOS transistor of a second conductivity type having a first terminal connected to said second terminal of said first MOS transistor, a second terminal connected to a reference potential, and a gate receiving said input signal; a third MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to a first connection node between said first terminal of said second MOS transistor and said second terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said third MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; a fifth MOS transistor of the first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to said first connection node; a sixth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said fifth MOS transistor, a second terminal connected to said reference potential, and a gate connected to a second connection node between said first terminal of said fourth MOS transistor and said second terminal of said third MOS transistor; a seventh MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving said input signal; an eighth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said seventh MOS transistor, a second terminal connected to a third connection node between said first terminal of said sixth MOS transistor and said second terminal of said fifth MOS transistor, and a gate connected to said potential source; a ninth MOS transistor of the second conductivity type having a first terminal connected to said first connection node, a second terminal, and a gate connected to a fourth connection node between said first terminal of said eighth MOS transistor and said second terminal of said seventh MOS transistor; a tenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said ninth MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; an eleventh MOS transistor having a first terminal connected to said first terminal of said ninth MOS transistor, a second terminal connected to said second terminal of said ninth MOS transistor, and a gate receiving said changing circuit control signal; a twelfth MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to a fifth connection node between said first terminal of said tenth MOS transistor and said second terminal ninth MOS transistor; a thirteenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said twelfth MOS transistor, a second terminal connected to said reference potential, and a gate connected to said third connection node; and a capacitor having a first terminal connected to said fifth connection node and a second terminal connected to a sixth connection node between said first terminal of said thirteenth MOS transistor and said second terminal of said twelfth MOS transistor.

Claim 8

A semiconductor device, comprising: a potential source having a first potential; an output buffer; a potential changing circuit coupled to said potential source and to said output buffer, said potential changing circuit responsive to a changing circuit control signal during one of a stress test operation and a normal operation for outputting said first potential to said output buffer and responsive to said changing circuit control signal during the other of the stress test operation and the normal operation for outputting a second potential different than said first potential to said output buffer; wherein said potential changing circuit comprises: a first MOS transistor of a first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving an input signal; a second MOS transistor of a second conductivity type having a first terminal connected to said second terminal of said first MOS transistor, a second terminal connected to a reference potential, and a gate receiving said input signal; a third MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to a first connection node between said first terminal of said second MOS transistor and said second terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said third MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; a fifth MOS transistor of the first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to said first connection node; a sixth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said fifth MOS transistor, a second terminal connected to said reference potential, and a gate connected to a second connection node between said first terminal of said fourth MOS transistor and said second terminal of said third MOS transistor; a seventh MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving said input signal; an eighth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said seventh MOS transistor, a second terminal connected to a third connection node between said first terminal of said sixth MOS transistor and said second terminal of said fifth MOS transistor, and a gate connected to said potential source; a ninth MOS transistor of the second conductivity type having a first terminal connected to said first connection node, a second terminal, and a gate connected to a fourth connection node between said first terminal of said eighth MOS transistor and said second terminal of said seventh MOS transistor; a tenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said ninth MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; an eleventh MOS transistor having a first terminal connected to said first terminal of said ninth MOS transistor, a second terminal connected to said second terminal of said ninth MOS transistor, and a gate receiving said changing circuit control signal; a twelfth MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to a fifth connection node between said first terminal of said tenth MOS transistor and said second terminal ninth MOS transistor; a thirteenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said twelfth MOS transistor, a second terminal connected to said reference potential, and a gate connected to said third connection node; and a capacitor having a first terminal connected to said fifth connection node and a second terminal connected to a sixth connection node between said first terminal of said thirteenth MOS transistor and said second terminal of said twelfth MOS transistor.

Claim 9

A semiconductor device, comprising: a potential source having a first potential; an output buffer; a potential changing circuit coupled to said potential source and to said output buffer, said potential changing circuit responsive to a changing circuit control signal during one of a stress test operation and a normal operation for outputting said first potential to said output buffer and responsive to said changing circuit control signal during the other of the stress test operation and the normal operation for outputting a second potential different than said first potential to said output buffer; wherein said potential changing circuit comprises: a first MOS transistor of a first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving an input signal; a second MOS transistor of a second conductivity type having a first terminal connected to said second terminal of said first MOS transistor, a second terminal connected to a reference potential, and a gate receiving said input signal; a third MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to a first connection node between said first terminal of said second MOS transistor and said second terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said third MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; a fifth MOS transistor of the first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to said first connection node; a sixth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said fifth MOS transistor, a second terminal connected to said reference potential, and a gate connected to a second connection node between said first terminal of said fourth MOS transistor and said second terminal of said third MOS transistor; a seventh MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving said input signal; an eighth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said seventh MOS transistor, a second terminal connected to a third connection node between said first terminal of said sixth MOS transistor and said second terminal of said fifth MOS transistor, and a gate connected to said potential source; a ninth MOS transistor of the second conductivity type having a first terminal connected to said first connection node, a second terminal, and a gate connected to a fourth connection node between said first terminal of said eighth MOS transistor and said second terminal of said seventh MOS transistor; a tenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said ninth MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; an eleventh MOS transistor of the first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving said changing circuit control signal; a twelfth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said eleventh MOS transistor, a second terminal, and a gate connected to a fifth connection node between said first terminal of sid tenth MOS transistor and said second terminal of said ninth MOS transistor; a thirteenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said twelfth MOS transistor, a second terminal connected to said reference potential, and a gate connected to said third connection node; and a capacitor having a first terminal connected to said fifth connection node and a second terminal connected to a sixth connection node between said first terminal of said thirteenth MOS transistor and said second terminal of said twelfth MOS transistor.

Claim 10

A semiconductor device, comprising: a potential source having a first potential; an output buffer; a potential changing circuit coupled to said potential source and to said output buffer, said potential changing circuit responsive to a changing circuit control signal during one of a stress test operation and a normal operation for outputting said first potential to said output buffer and responsive to said changing circuit control signal during the other of the stress test operation and the normal operation for outputting a second potential different than said first potential to said output buffer; wherein said potential changing circuit comprises: a first MOS transistor of a first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving an input signal; a second MOS transistor of a second conductivity type having a first terminal connected to said second terminal of said first MOS transistor, a second terminal connected to a reference potential, and a gate receiving said input signal; a third MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to a first connection node between said first terminal of said second MOS transistor and said second terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said third MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; a fifth MOS transistor of the first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate connected to said first connection node; a sixth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said fifth MOS transistor, a second terminal connected to said reference potential, and a gate connected to a second connection node between said first terminal of said fourth MOS transistor and said second terminal of said third MOS transistor; a seventh MOS transistor of the second conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving said input signal; an eighth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said seventh MOS transistor, a second terminal connected to a third connection node between said first terminal of said sixth MOS transistor and said second terminal of said fifth MOS transistor, and a gate connected to said potential source; a ninth MOS transistor of the second conductivity type having a first terminal connected to said first connection node, a second terminal, and a gate connected to a fourth connection node between said first terminal of said eighth MOS transistor and said second terminal of said seventh MOS transistor; a tenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said ninth MOS transistor, a second terminal connected to said reference potential, and a gate receiving said input signal; an eleventh MOS transistor of the first conductivity type having a first terminal connected to said potential source, a second terminal, and a gate receiving said changing circuit control signal; a twelfth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said eleventh MOS transistor, a second terminal, and a gate connected to a fifth connection node between said first terminal of sid tenth MOS transistor and said second terminal of said ninth MOS transistor; a thirteenth MOS transistor of the second conductivity type having a first terminal connected to said second terminal of said twelfth MOS transistor, a second terminal connected to said reference potential, and a gate connected to said third connection node; and a capacitor having a first terminal connected to said fifth connection node and a second terminal connected to a sixth connection node between said first terminal of said thirteenth MOS transistor and said second terminal of said twelfth MOS transistor.

Claim 11

A semiconductor device, comprising: a potential boosting circuit which is applied with a first power-supply potential during a normal operation of said semiconductor device and outputs a second power-supply potential by internally boosting said first power-supply potential in response to a boosting enable signal during the normal operation, and which is applied with a third power-supply potential during a voltage stress test of said semiconductor device and outputs said third power-supply potential in response to a boosting disable signal during the voltage stress test; a first circuit block applied with said first power-supply potential during the normal operation and applied with said third power-supply potential during the voltage stress test; and a second circuit block applied with said second power-supply potential from said potential boosting circuit during the normal operation and applied with said third power-supply potential from said potential boosting circuit during the voltage stress test.

Claim 12

A semiconductor device, comprising: a potential boosting circuit which is applied with a first power-supply potential during a normal operation of said semiconductor device and outputs a second power-supply potential by internally boosting said first power-supply potential in response to a boosting enable signal during the normal operation, and which is applied with a third power-supply potential during a voltage stress test of said semiconductor device and outputs said third power-supply potential in response to a boosting disable signal during the voltage stress test; a first circuit block applied with said first power-supply potential during the normal operation and applied with said third power-supply potential during the voltage stress test; and a second circuit block applied with said second power-supply potential from said potential boosting circuit during the normal operation and applied with said third power-supply potential from said potential boosting circuit during the voltage stress test.

Claim 13

The semiconductor device according to claim 6, wherein said third power-supply potential is higher than said first power-supply potential.

Claim 14

The semiconductor device according to claim 6, wherein said first power-supply potential and said third power-supply potential are externally applied potentials.

Claim 15

The semiconductor device according to claim 6, wherein said first power-supply potential and said third power-supply potential are internal potentials generated by lowering externally applied potentials.

Claim 16

A semiconductor device, comprising: a potential lowering circuit which is applied with a first power-supply potential during a normal operation of said semiconductor device and outputs a second power-supply potential by internally lowering said first power-supply potential in response to a lowering enable signal during the normal operation, and which is applied with a third power-supply potential during a voltage stress test of said semiconductor device and outputs said third power-supply potential in response to a lowering disable signal during the voltage stress test; a first circuit block applied with said first power-supply potential during the normal operation and applied with said third power-supply potential during the voltage stress test; and a second circuit block applied with said second power-supply potential from said potential lowering circuit during the normal operation and applied with said third power-supply potential from said potential lowering circuit during the voltage stress test.

Claim 17

A semiconductor device, comprising: a potential lowering circuit which is applied with a first power-supply potential during a normal operation of said semiconductor device and outputs a second power-supply potential by internally lowering said first power-supply potential in response to a lowering enable signal during the normal operation, and which is applied with a third power-supply potential during a voltage stress test of said semiconductor device and outputs said third power-supply potential in response to a lowering disable signal during the voltage stress test; a first circuit block applied with said first power-supply potential during the normal operation and applied with said third power-supply potential during the voltage stress test; and a second circuit block applied with said second power-supply potential from said potential lowering circuit during the normal operation and applied with said third power-supply potential from said potential lowering circuit during the voltage stress test.

Claim 18

The semiconductor device according to claim 10, wherein said third power-supply potential is equal to said first power-supply potential.

Claim 19

The semiconductor device according to claim 10, wherein said first power-supply potential and said third power-supply potential are externally applied potentials.

Claim 20

The semiconductor device according to claim 10, wherein said first power-supply potential and said third power-supply potential are internal potentials generated by lowering externally applied potentials.

Claim 21

A semiconductor device according to any one of claims 6, 7, 8, and 9, further comprising a memory cell and a word line connected to said memory call, wherein said second circuit block includes a word line driving circuit for driving and said word line; and said potential boosting circuit is a word line potential boosting circuit for outputting said second power-supply potential to said word line driving circuit.

Claim 22

A semiconductor device according to any one of claims 6, 7, 8, and 9, further comprising a memory cell and a word line connected to said memory cell, wherein said second circuit block includes an output buffer; and said potential boosting circuit outputs said second power-supply potential to said output buffer.

Claim 23

A semiconductor device according to any one of claims 10, 11, 12, and 13, further comprising a memory cell and a word line connected to said memory cell, wherein said first circuit block includes a word line driving circuit for driving said word line.

Claim 24

A semiconductor device according to any one of claims 10, 11, 12, and 13, further comprising a memory cell and a word line connected to said memory cell, wherein said first circuit block includes an output buffer.