US5426772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single PAL circuit generating system clock and control signals to minimize skew
Assignee: Intel Corp
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Filing: 1993-08-16
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Granted: 1995-06-20
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Expires: 2013-08-16
Abstract
Abstract The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to random access memory devices thereby improving system performance. A clock PAL is programmed to function as an asynchronous state machine to generate the clock signals and the memory device chip select. A clock source from an oscillator is input to the PAL. This clock source is buffered by the PAL and presented at the PAL outputs as the system clock. The memory device chip select is also generated inside this PAL using the source clock and other signals generated inside the PAL.
Inventors
- 👤 Gary Brady
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:53
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
225 words
A circuit for substantially eliminating skew between a system clock signal and memory control signals in a microprocessor system, said microprocessor system including a random access memory (19) coupled to a microprocessor (15) over an address and data bus, and an oscillator 925), said circuit comprising: a) a PAL (29) coupled to said oscillator for receiving a clocking signal generated by said oscillator, said PAL being programmed to generate at least one clock signal for use by said microprocessor (15) and at least one control signal for use by said random access memory (19), wherein said oscillator clocking signal has the same frequency as said at least one clock signal, said at least one control signal has a frequency which is different than the frequency of said at least one clock signal, and said at least one clock signal and said at least one control signal are synchronized such that the skew between said at least one clock signal and the at least one control signal is less than 2 ns at the end of a 40 ns clock period such that said random access memory operates with zero waitstates; b) a buffer means (31) coupled between said PAL, said microprocessor and said random access memory for buffering said at least one clock signal and said at least one control signal generated by said PAL.
Claim 2
Dependent Claim
225 words
A circuit for substantially eliminating skew between a system clock signal and memory control signals in a microprocessor system, said microprocessor system including a random access memory (19) coupled to a microprocessor (15) over an address and data bus, and an oscillator 925), said circuit comprising: a) a PAL (29) coupled to said oscillator for receiving a clocking signal generated by said oscillator, said PAL being programmed to generate at least one clock signal for use by said microprocessor (15) and at least one control signal for use by said random access memory (19), wherein said oscillator clocking signal has the same frequency as said at least one clock signal, said at least one control signal has a frequency which is different than the frequency of said at least one clock signal, and said at least one clock signal and said at least one control signal are synchronized such that the skew between said at least one clock signal and the at least one control signal is less than 2 ns at the end of a 40 ns clock period such that said random access memory operates with zero waitstates; b) a buffer means (31) coupled between said PAL, said microprocessor and said random access memory for buffering said at least one clock signal and said at least one control signal generated by said PAL.
Claim 3
Dependent Claim
28 words
The circuit defined by claim 1 wherein the at least one clock signal for use by said microprocessor has the same frequency as the frequency of said oscillator.
Claim 4
Dependent Claim
18 words
The circuit defined by claim 1 wherein said PAL is programmed utilizing asynchronous state machines and asynchronous logic.
Claim 5
Dependent Claim
69 words
The circuit defined by claim 1 wherein said PAL is programmed according to PAL equations such that a memory chip select signal, SRAMCS, is generated by the equation: ##EQU2## and the CLKSO signal is generated by the equation: ##EQU3## and the TDATCYC signal is generated by the equation: ##EQU4## and the CLK signal is generated by the equation: ##EQU5## and the CLK2 signal is generated by the equation: CLK2=ICLK.
Claim 6
Dependent Claim
40 words
The circuit defined by claim 1 further comprising control logic means (17) coupled to said microprocessor, said buffer means and said random access memory for generating additional control signals to control read and write accesses to said random access memory.
Claim 7
Dependent Claim
63 words
The circuit defined by claim 1 wherein trace routings of said at least one clock signal and said at least one control signal are created so that the trace length of the at least one control signal is less than or equal to the trace length of the at least one clock signal and the trace length of said address and data bus.
Claim 8
Dependent Claim
236 words
A circuit for substantially eliminating skew between a system clock signal and memory control signals in a microprocessor system, said microprocessor system including a static random access memory coupled to a microprocessor over an address and data bus, and an oscillator, said circuit comprising: a) a PAL coupled to said oscillator for receiving a clocking signal generated by said oscillator, said PAL being programmed to generate at least one cock signal generated by said oscillator, said PAL being programmed to generate at least one clock signal for use by said microprocessor and at least one control signal for use by said random access memory, wherein said oscillator clocking signal has the same frequency as said at least one clock signal, said at least one control signal has a frequency which is different than the frequency of said at least one clock signal, and said at least one clock signal and said at least one control signal are synchronized such that the skew between said at least one clock signal and the at least one control signal is less than 2 ns at the end of a 40 ns clock period such that said static random acces memory operates with zero waitstates; b) a buffer means (31) coupled between said PAL, said microprocessor and said random access memory for buffering said at least one clock signal and said at least one control signal generated by said PAL.
Claim 9
Dependent Claim
236 words
A circuit for substantially eliminating skew between a system clock signal and memory control signals in a microprocessor system, said microprocessor system including a static random access memory coupled to a microprocessor over an address and data bus, and an oscillator, said circuit comprising: a) a PAL coupled to said oscillator for receiving a clocking signal generated by said oscillator, said PAL being programmed to generate at least one cock signal generated by said oscillator, said PAL being programmed to generate at least one clock signal for use by said microprocessor and at least one control signal for use by said random access memory, wherein said oscillator clocking signal has the same frequency as said at least one clock signal, said at least one control signal has a frequency which is different than the frequency of said at least one clock signal, and said at least one clock signal and said at least one control signal are synchronized such that the skew between said at least one clock signal and the at least one control signal is less than 2 ns at the end of a 40 ns clock period such that said static random acces memory operates with zero waitstates; b) a buffer means (31) coupled between said PAL, said microprocessor and said random access memory for buffering said at least one clock signal and said at least one control signal generated by said PAL.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |