US5426650A
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US
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Full scan optimization technique using drive one/drive zero elements and multiple capture clocking
Assignee: Advanced Micro Devices Inc
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Filing: 1994-07-11
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Granted: 1995-06-20
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Expires: 2014-07-11
Abstract
Abstract A test circuit and test technique for scan testing integrated circuits is disclosed. The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistors than conventional scan latches. The testing technique utilizes the clock input to the latches in the ICs for propagating data through the latches. The test circuit and test techniques may be used with microprocessors and particularly RISC microprocessors. The test technique includes coupling a drive 1 or drive 0 element to a logic element coupled to a general latch. The drive 1 or drive 0 scan element allows the general latch to be clocked by a clock signal such as a φ1 clock signal or φ2 clock signal.
Inventors
- 👤 Gopi Ganapathy
- 👤 Robert Thaden
- 👤 Steve Horne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:08
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/31858; G01R31/318541
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
224 words
In an integrated circuit including a circuit formed by a plurality of circuit elements, at least some of said circuit elements being sequential circuit elements with at least one of said sequential circuit elements being clocked at a clock input by a combination of a data signal and a system clock during normal operation, the improvement of a test arrangement enabling said sequential elements to be tested and comprising: gate means having an output coupled to said clock input, said gate means having a first gate input and having a second gate input, said first gate input for receiving said system clock; and test mode means having an output coupled to said second gate input, a first test input for receiving said data signal and a second test input for receiving a test mode signal, said test mode means conveying a steady state control signal to said second gate input responsive to said test mode signal to cause said at least one sequential circuit element to be clocked by said system clock alone and for conveying said data signal to said second gate input in the absence of said test mode signal to cause said at least one sequential element to be clocked by the combination of said system clock and said data signal, wherein said steady state control signal is a non-programmable signal.
Claim 2
Dependent Claim
224 words
In an integrated circuit including a circuit formed by a plurality of circuit elements, at least some of said circuit elements being sequential circuit elements with at least one of said sequential circuit elements being clocked at a clock input by a combination of a data signal and a system clock during normal operation, the improvement of a test arrangement enabling said sequential elements to be tested and comprising: gate means having an output coupled to said clock input, said gate means having a first gate input and having a second gate input, said first gate input for receiving said system clock; and test mode means having an output coupled to said second gate input, a first test input for receiving said data signal and a second test input for receiving a test mode signal, said test mode means conveying a steady state control signal to said second gate input responsive to said test mode signal to cause said at least one sequential circuit element to be clocked by said system clock alone and for conveying said data signal to said second gate input in the absence of said test mode signal to cause said at least one sequential element to be clocked by the combination of said system clock and said data signal, wherein said steady state control signal is a non-programmable signal.
Claim 3
Dependent Claim
31 words
The test arrangement of claim 1, further comprising a latch means having a latch input coupled to said first test input of said test mode means for storing said data signal.
Claim 4
Dependent Claim
78 words
The test arrangement of claim 2, wherein the latch means comprises: a shift mode input; a shift register output; a transfer gate having a control input coupled to the shift mode input, an output coupled to said latch input, and a data input; and wherein the transfer gate allows the signal at said data input of the transfer gate to be applied to said latch input when a shift mode signal is present on the shift mode input.
Claim 5
Dependent Claim
75 words
The test arrangement of claim 3, further comprising: a capture mode input; a capture transfer gate having a control input coupled to said capture mode input, a capture data input coupled to said first test input, and an output coupled to said latch input, wherein the capture transfer gate allows the data signal on said first test input to be applied to said latch input when a signal on the capture mode input is present.
Claim 6
Dependent Claim
75 words
The test arrangement of claim 2, further comprising: a capture mode input; a capture transfer gate having a control input coupled to said capture mode input, a capture data input coupled to said first test input, and an output coupled to said latch input, wherein the capture transfer gate allows the data signal on said first test input to be applied to said latch input when a signal on the capture mode input is present.
Claim 7
Dependent Claim
22 words
The test arrangement of claim 1, wherein the steady state is a logic high and the gate means is an AND gate.
Claim 8
Dependent Claim
24 words
The test arrangement of claim 1, wherein the gate means is an OR function gate and the steady state signal is a logic low.
Claim 9
Dependent Claim
64 words
The integrated circuit of claim 1 wherein the test mode means includes an FET having a drain, a source, and a gate, said drain being coupled to a ground level or a power level representative of the steady state control signal and said source being coupled to said output of said test mode means and said gate being coupled to said second test input.
Claim 10
Dependent Claim
157 words
A drive element for use in scan testing an integrated circuit having sequential elements, the drive element comprising: a data input; a data output; a test mode input which receives a test mode signal indicative of a system mode or a test mode; a transfer gate coupled between the data input and the data output, the transfer gate being controlled by the test mode input so that the transfer gate allows data to pass from the data input to the data output when the integrated circuit is in the system mode; and a transistor for driving a fixed predetermined logic level at the data output when the system is in the test mode, the transistor having a gate coupled to the test mode input, a drain coupled to the predetermined logic level, and a source coupled to the data output wherein the fixed predetermined logic level is permanently set to a logic high or logic low level.
Claim 11
Dependent Claim
157 words
A drive element for use in scan testing an integrated circuit having sequential elements, the drive element comprising: a data input; a data output; a test mode input which receives a test mode signal indicative of a system mode or a test mode; a transfer gate coupled between the data input and the data output, the transfer gate being controlled by the test mode input so that the transfer gate allows data to pass from the data input to the data output when the integrated circuit is in the system mode; and a transistor for driving a fixed predetermined logic level at the data output when the system is in the test mode, the transistor having a gate coupled to the test mode input, a drain coupled to the predetermined logic level, and a source coupled to the data output wherein the fixed predetermined logic level is permanently set to a logic high or logic low level.
Claim 12
Dependent Claim
15 words
The drive element of claim 9, wherein the predetermined logic level is a ground level.
Claim 13
Dependent Claim
16 words
The drive element of claim 9, wherein the predetermined logic level is a positive five volts.
Claim 14
Dependent Claim
56 words
The drive element of claim 9 wherein the transistor includes a drain terminal, a source terminal, and a gate terminal, the drain terminal being coupled to a logic level indicative of the fixed predetermined logic level, the source terminal being coupled to the data output, and the gate terminal being coupled to the test mode input.
Claim 15
Dependent Claim
90 words
The drive element of claim 9, further comprising: a shift register input; a capture mode input; a shift mode input; a shift register output; and a latch element coupled to the data input and the shift register input, the latch element receiving data from the shift register input when a signal is present on the shift mode input and receiving data from the data input when a signal is present on the capture mode input, the latch element providing a representation of the received data to the shift register output.
Claim 16
Dependent Claim
22 words
The drive element of claim 13, further comprising a shift transfer gate coupled between the latch element and the shift register input.
Claim 17
Dependent Claim
21 words
The drive element of claim 13, further comprising a capture transfer gate coupled between the latch element and the data input.
Claim 18
Dependent Claim
142 words
In an integrated circuit including a circuit formed by a plurality of circuit elements, at least some of said circuit elements being sequential circuit elements which are clocked by a system clock with at least one of said sequential circuit elements being clocked at a clock input by a combination of both a logic signal and said system clock during normal operation, the improvement comprising test mode means responsive to a test mode signal for driving a predetermined steady state signal and causing said at least one sequential circuit element to be clocked by said system clock alone and being responsive to the absence of said test mode signal to cause said at least one sequential element to be clocked by the combination of said system clock and said logic signal, wherein in the predetermined steady state signal is a non-programmable signal.
Claim 19
Dependent Claim
142 words
In an integrated circuit including a circuit formed by a plurality of circuit elements, at least some of said circuit elements being sequential circuit elements which are clocked by a system clock with at least one of said sequential circuit elements being clocked at a clock input by a combination of both a logic signal and said system clock during normal operation, the improvement comprising test mode means responsive to a test mode signal for driving a predetermined steady state signal and causing said at least one sequential circuit element to be clocked by said system clock alone and being responsive to the absence of said test mode signal to cause said at least one sequential element to be clocked by the combination of said system clock and said logic signal, wherein in the predetermined steady state signal is a non-programmable signal.
Claim 20
Dependent Claim
31 words
The test arrangement of claim 16, further comprising a latch means coupled to said test mode means for storing an inverted or non-inverted signal an input of said test mode means.
Claim 21
Dependent Claim
79 words
The test arrangement of claim 17, further comprising: a capture mode input; a capture transfer gate having a control input coupled to capture mode input, an input coupled to said input of said test mode means, and an output coupled to said latch means, wherein the capture transfer gate allows the signal on said input of said test mode means to be applied to said input of said latch when a signal on the capture mode input is present.
Claim 22
Dependent Claim
60 words
The integrated circuit of claim 16 wherein the test mode means includes a transistor having a drain terminal directly coupled to a logic level indicative of the predetermined steady state signal, a source terminal directly coupled to an output of the test mode means, and a gate terminal coupled to receive a control signal indicative of the test mode signal.
Claim 23
Dependent Claim
193 words
A drive scan latch for use in an integrated circuit, comprising: a scan latch input for receiving a data signal; a scan latch output; test mode means, coupled between the scan latch input and the scan latch output, for providing an output signal at a predetermined logic level at the scan latch output when a test signal is present and providing the data signal at the scan latch input to the scan latch output when the test signal is absent wherein the predetermined logic level is permanently assigned when the drive scan latch is fabricated, a shift register input; a capture mode input; a shift mode input; a shift register output; a latch element coupled to the scan latch input and the shift register input, the latch element receiving data from the shift register input when a signal is present on the shift mode input and receiving data from the scan latch input when a signal is present on the capture mode input, the latch element providing a representation of the received data to the shift register output; and a shift transfer gate coupled between the latch element and the shift register input.
Claim 24
Dependent Claim
193 words
A drive scan latch for use in an integrated circuit, comprising: a scan latch input for receiving a data signal; a scan latch output; test mode means, coupled between the scan latch input and the scan latch output, for providing an output signal at a predetermined logic level at the scan latch output when a test signal is present and providing the data signal at the scan latch input to the scan latch output when the test signal is absent wherein the predetermined logic level is permanently assigned when the drive scan latch is fabricated, a shift register input; a capture mode input; a shift mode input; a shift register output; a latch element coupled to the scan latch input and the shift register input, the latch element receiving data from the shift register input when a signal is present on the shift mode input and receiving data from the scan latch input when a signal is present on the capture mode input, the latch element providing a representation of the received data to the shift register output; and a shift transfer gate coupled between the latch element and the shift register input.
Claim 25
Dependent Claim
22 words
The drive scan latch of claim 20, further comprising a capture transfer gate coupled between the latch element and the data input.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |