US5426392A
Expired / Lapsed
US
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Spread clock source for reducing electromagnetic interference generated by digital circuits
Assignee: Qualcomm Inc
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Filing: 1994-09-21
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Granted: 1995-06-20
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Expires: 2014-09-21
Abstract
Abstract In a digital circuit in which electromagnetic interference is generated at the fundamental and harmonic frequencies of the digital circuit clock source, a clock source for reducing the peak spectral content of said interference. The clock source includes a noise source for generating a broad band frequency noise signal and a filter circuit for receiving and bandpass filtering the noise signal and providing the filtered noise signal as the clock signal.
Inventors
- 👤 Richard K. Kornfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:58
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03B; H03B29/00; H04; H04B; H04B15/00; H04B15/02; H04B15/04; H04B2215/00; H04B2215/064; H04B2215/067
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
104 words
A clock source, in a digital circuit, for generating a clock signal having noise modulated fundamental and harmonic frequencies, the clock signal having a reduced peak spectral content, the clock source comprising: a noise diode having a first terminal coupled to a bias voltage and a second terminal coupled to a ground potential, the noise diode generating a noise signal in response to the bias voltage; and a bandpass filter having an input and an output, the input coupled to the first terminal, the bandpass filter filtering the noise signal such that the bandpass filter generates the clock signal at the bandpass filter output.
Claim 2
Dependent Claim
104 words
A clock source, in a digital circuit, for generating a clock signal having noise modulated fundamental and harmonic frequencies, the clock signal having a reduced peak spectral content, the clock source comprising: a noise diode having a first terminal coupled to a bias voltage and a second terminal coupled to a ground potential, the noise diode generating a noise signal in response to the bias voltage; and a bandpass filter having an input and an output, the input coupled to the first terminal, the bandpass filter filtering the noise signal such that the bandpass filter generates the clock signal at the bandpass filter output.
Claim 3
Dependent Claim
89 words
A clock source for generating a digital clock signal at a nominal frequency having a reduced discrete harmonic spectral content, the clock source comprising: a waveform generator for providing a waveform at the nominal frequency; a noise generator for generating a noise signal; a summer, coupled to the waveform generator and the noise generator, for combining the waveform and the noise signal to produce a noisy waveform; and a comparator for providing the digital clock signal as a function of the noisy waveform as compared to a reference value.
Claim 4
Dependent Claim
89 words
A clock source for generating a digital clock signal at a nominal frequency having a reduced discrete harmonic spectral content, the clock source comprising: a waveform generator for providing a waveform at the nominal frequency; a noise generator for generating a noise signal; a summer, coupled to the waveform generator and the noise generator, for combining the waveform and the noise signal to produce a noisy waveform; and a comparator for providing the digital clock signal as a function of the noisy waveform as compared to a reference value.
Claim 5
Dependent Claim
17 words
The clock source of claim 2 wherein the waveform and the noise signal are both analog signals.
Claim 6
Dependent Claim
13 words
The clock source of claim 2 wherein the waveform has a controllable amplitude.
Claim 7
Dependent Claim
14 words
The clock source of claim 2 wherein the noise signal has a controllable amplitude.
Claim 8
Dependent Claim
17 words
The clock source of claim 2 wherein the waveform and the noise signal are both digital signals.
Claim 9
Dependent Claim
15 words
The dock source of claim 6 wherein the noise signal is a pseudo random code.
Claim 10
Dependent Claim
74 words
A clock source for generating a clock signal at a nominal frequency having a reduced discrete harmonic spectral content, the clock source comprising: means for providing a digital signal at the nominal frequency; single bit generation means for providing a randomly switching signal; and one-shot circuitry for providing the clock signal by providing an edge transition following each edge transition of the random switching signal which follows an edge transition of the digital signal.
Claim 11
Dependent Claim
74 words
A clock source for generating a clock signal at a nominal frequency having a reduced discrete harmonic spectral content, the clock source comprising: means for providing a digital signal at the nominal frequency; single bit generation means for providing a randomly switching signal; and one-shot circuitry for providing the clock signal by providing an edge transition following each edge transition of the random switching signal which follows an edge transition of the digital signal.
Claim 12
Dependent Claim
65 words
A clock source for generating a clock signal at a nominal frequency having a reduced discrete harmonic spectral content, the clock source comprising: means for providing a digital signal at the nominal frequency; means for providing random signal generation; and a variable delay line for receiving the digital signal and delaying the digital signal in response to the random signal and providing the clock signal.
Claim 13
Dependent Claim
65 words
A clock source for generating a clock signal at a nominal frequency having a reduced discrete harmonic spectral content, the clock source comprising: means for providing a digital signal at the nominal frequency; means for providing random signal generation; and a variable delay line for receiving the digital signal and delaying the digital signal in response to the random signal and providing the clock signal.
Claim 14
Dependent Claim
71 words
A clock source for generating a clock signal having a reduced discrete harmonic spectral content, the clock source comprising: a clock generator circuit for generating an initial clock signal; a noise source for generating a noise signal; and a digital divider, coupled to the clock generator and the noise source, for generating the clock signal from the initial clock signal in response to the noise signal and a predetermined divide ratio.
Claim 15
Dependent Claim
71 words
A clock source for generating a clock signal having a reduced discrete harmonic spectral content, the clock source comprising: a clock generator circuit for generating an initial clock signal; a noise source for generating a noise signal; and a digital divider, coupled to the clock generator and the noise source, for generating the clock signal from the initial clock signal in response to the noise signal and a predetermined divide ratio.
Claim 16
Dependent Claim
28 words
The clock source of claim 10 wherein the digital divider divides the initial clock signal by a divide number comprising the noise signal and the predetermined divide ratio.
Claim 17
Dependent Claim
33 words
The clock source of claim 11 wherein the noise signal provides the least significant bits of the divide number and the predetermined divide ratio provides the most significant bits of the divide number.
Claim 18
Dependent Claim
75 words
A clock source for generating a clock signal having a reduced discrete harmonic spectral content, the clock source comprising: a clock generator circuit for generating an initial clock signal; a pseudo noise source for generating a pseudo noise signal; and a digital divider, coupled to the clock generator and the pseudo noise source, for generating the clock signal from the initial clock signal in response to the pseudo noise signal and a predetermined divide ratio.
Claim 19
Dependent Claim
75 words
A clock source for generating a clock signal having a reduced discrete harmonic spectral content, the clock source comprising: a clock generator circuit for generating an initial clock signal; a pseudo noise source for generating a pseudo noise signal; and a digital divider, coupled to the clock generator and the pseudo noise source, for generating the clock signal from the initial clock signal in response to the pseudo noise signal and a predetermined divide ratio.
Claim 20
Dependent Claim
29 words
The clock source of claim 13 wherein the digital divider divides the initial clock signal by a divide number comprising the pseudo noise signal and the predetermined divide ratio.
Claim 21
Dependent Claim
34 words
The clock source of claim 14 wherein the pseudo noise signal provides the least significant bits of the divide number and the predetermined divide ratio provides the most significant bits of the divide number.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |