US5425034A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated logic circuit with internal circuit to be examined by scan path test method
Assignee: Renesas Electronics Corp
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Filing: 1992-10-28
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Granted: 1995-06-13
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Expires: 2012-10-28
Abstract
Abstract A semiconductor integrated logic circuit making it feasible to perform different testing methods including a scan path test method while retaining a minimized number of an excluseive external terminal for testing. A first internal logic circuit comprises first flip-flop circuits which operate either in a logic operation mode or in a shift register operation mode through an operation mode control signal. At least one second flip-flop circuit is connected to the input side of the first internal logic circuit, which does not participate in the logic operation of the first internal logic circuit and can operate as a shift register together with the first flip-flop circuits. A second internal logic circuit receives the control signal and the output signal of the second flip-flop circuit and performs a predetermined logic such as an OR logic between the signals to thereby generate and output a testing control signal.
Inventors
- 👤 Hideharu Ozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318555
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
351 words
A semiconductor integrated logic circuit which performs a given logic operatioin, said circuit comprising: (a) a first internal logic circuit containing a plurality of first flip-flop circuits; said plurality of first flip-flop circuits operating in either a logic operation mode or a shift register mode, said logic operation mode and said shift register mode being selected in response to an operation mode control signal; said plurality of first flip-slop circuits performing said given logic operation of said semiconductor integrated logic circuit while in said logic operation mode; said plurality of first flip-flop circuits operating as a first shift register while in said shift register mode; (b) a second flip-flop circuit coupled to an input side of said first internal logic circuit; said second flip-flop circuit being connected to said plurality of first flip-flop circuits in order to operate as a second shift register while in said shift register mode; said second flip-flop circuit not being used for said given logic operation of said semiconductor integrated logic circuit while in said logic operation mode; and (c) a second internal logical circuit for receiving said operation mode control signal and an output signal of said second flip-flop circuit; said second internal logic circuit performing a logic operation to output a testig control signal responsive to logic states of said operation mode control signal and said output signal of said second flip-flop circuit; said second internal logic circuit not being used for said given operation of said semiconductor integrated logic circuit while in said logic operation mode; said testing control signal being able to be used for testing said semiconductor integrated logic circuit; wherein (d) on testing said plurality of first flip-flop circuits, said plurality of first flip-flop circuits are switched to said shift register mode in response to said operation mode control signal so that said plurality of first flip-flop circuits and said second flip-flop circuit act as said second shift register; a testing input signal being supplied to an input end of said second shift register and a testing output signal being derived from an output end of said second shift register.
Claim 2
Dependent Claim
351 words
A semiconductor integrated logic circuit which performs a given logic operatioin, said circuit comprising: (a) a first internal logic circuit containing a plurality of first flip-flop circuits; said plurality of first flip-flop circuits operating in either a logic operation mode or a shift register mode, said logic operation mode and said shift register mode being selected in response to an operation mode control signal; said plurality of first flip-slop circuits performing said given logic operation of said semiconductor integrated logic circuit while in said logic operation mode; said plurality of first flip-flop circuits operating as a first shift register while in said shift register mode; (b) a second flip-flop circuit coupled to an input side of said first internal logic circuit; said second flip-flop circuit being connected to said plurality of first flip-flop circuits in order to operate as a second shift register while in said shift register mode; said second flip-flop circuit not being used for said given logic operation of said semiconductor integrated logic circuit while in said logic operation mode; and (c) a second internal logical circuit for receiving said operation mode control signal and an output signal of said second flip-flop circuit; said second internal logic circuit performing a logic operation to output a testig control signal responsive to logic states of said operation mode control signal and said output signal of said second flip-flop circuit; said second internal logic circuit not being used for said given operation of said semiconductor integrated logic circuit while in said logic operation mode; said testing control signal being able to be used for testing said semiconductor integrated logic circuit; wherein (d) on testing said plurality of first flip-flop circuits, said plurality of first flip-flop circuits are switched to said shift register mode in response to said operation mode control signal so that said plurality of first flip-flop circuits and said second flip-flop circuit act as said second shift register; a testing input signal being supplied to an input end of said second shift register and a testing output signal being derived from an output end of said second shift register.
Claim 3
Dependent Claim
41 words
The circuit as claimed in claim 1, wherein a logic of said second internal logic circuit is set so that said testing control signal from said second internal logic circuit varies corresponding to an output signal of said second flip-flop circuit.
Claim 4
Dependent Claim
17 words
The circuit as claimed in claim 2, wherein said second internal logic circuit is an OR logic.
Claim 5
Dependent Claim
35 words
The circuit as claimed in claim 1, wherein there are a plurality of said second flip-flop circuits, and a plurality of said second internal logic circuits corresponding to said plurality of said second flip-flop circuits.
Claim 6
Dependent Claim
56 words
The circuit as claimed in claim 1, further comprising a third internal logic circuit; said third internal logic circuit operating in a second logic operation mode and a test operation mode, said second logic operation mode and said test operation mode being selected in response to said testing control signal from said second internal logic circuit.
Claim 7
Dependent Claim
74 words
The circuit as claimed in claim 5, wherein said testing control signal from said second internal logic circuit is used for separating said third internal logical circuit; a testing input signal being supplied through a first external terminal of said semiconductor integrated logic circuit to said third internal logic circuit; and a testing output signal being derived through a second external terminal of said semiconductor integrated logic circuit from said third internal logic circuit.
Claim 8
Dependent Claim
34 words
The circuit as claimed in claim 5, wherein said testing control signal from said second internal logic circuit is used for separating said third internal logic circuit to test said third internal logic circuit.
Claim 9
Dependent Claim
26 words
The circuit as claimed in claim 1, wherein said second flip-flop circuit and said plurality of said first flip-flop circuits are the same type of circuit.
Claim 10
Dependent Claim
84 words
The circuit as claimed in claim 1, wherein a scan path test input signal is generated as said testing input signal in response to a testing of said plurality of first flip-flop circuits while in said shift register mode, and said generated scan path test input signal is supplied to said input end of said second shift register, and a scan path test output signal is generated as said testing output signal is being derived from said output end of said second shift register.
Claim 11
Dependent Claim
97 words
The circuit as claimed in claim 1, wherein a clock signal is supplied to said plurality of first flip-flop circuits and to said secind flip-flop circuit when testing said plurality of first flip-flop circuits while in said shift register mode; a scan path test input signal being supplied as said testing input signal to said input end of said second shift register in synchronization with said clock signal; and a scan path test output signal being generated as said testing output signal at said output end of said second shift register in synchronization with said clock signal.
Claim 12
Dependent Claim
250 words
A semiconductor integrated logic circuit comprising: a first internal logic circuit (11) operating in a logic operation mode and a test operation mode; a data input terminal (6) for receiving a data input signal; a clock input terminal (7) for receiving a clock signal; a control input terminal (8) for receiving a mode control signal, said mode control signal having first and second states; a data output terminal (12) for outputting a data output signal; a first register (1) for storing and outputting said data input signal in response to said clock signal; a second register (2) for storing and outputting an output from said first register to said data output terminal in response to said clock signal; said first internal logic circuit operating in said test operation mode in response to said mode control signal being in said first state, said first and second registers being connected to each other to form a shift register, said shift register storing and sequentially outputting said data input signal to said data output terminal; said first internal logic circuit operating in said logic operation mode in response to said mode control signal being in said second state, said first internal logic circuit being coupled to receive said output from said first register to perform a given logic operation of said semiconductor integrated logic circuit; and a second internal logic circuit (9) for outputting a testing control signal in response to said mode control signal and an output signal of said first register.
Claim 13
Dependent Claim
250 words
A semiconductor integrated logic circuit comprising: a first internal logic circuit (11) operating in a logic operation mode and a test operation mode; a data input terminal (6) for receiving a data input signal; a clock input terminal (7) for receiving a clock signal; a control input terminal (8) for receiving a mode control signal, said mode control signal having first and second states; a data output terminal (12) for outputting a data output signal; a first register (1) for storing and outputting said data input signal in response to said clock signal; a second register (2) for storing and outputting an output from said first register to said data output terminal in response to said clock signal; said first internal logic circuit operating in said test operation mode in response to said mode control signal being in said first state, said first and second registers being connected to each other to form a shift register, said shift register storing and sequentially outputting said data input signal to said data output terminal; said first internal logic circuit operating in said logic operation mode in response to said mode control signal being in said second state, said first internal logic circuit being coupled to receive said output from said first register to perform a given logic operation of said semiconductor integrated logic circuit; and a second internal logic circuit (9) for outputting a testing control signal in response to said mode control signal and an output signal of said first register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-12 | 1998-12-12 | 1999-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-12 | 2002-12-12 | 2003-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-12 | 2006-12-12 | 2007-06-13 | $7700.00 | Window Closed / Lapsed |