Non-volatile semiconductor memory having switching devices for segmentation of a memory page and a method thereof

Claim 1

A semiconductor memory array that includes a plurality of bit lines disposed in a first direction and a plurality of word lines disposed in a second direction transverse to the first direction such that each of the word lines overlaps each of the bit lines, a data storage cell being associated with each overlap of a word line and a bit line to define a plurality of rows and a plurality of columns of such data storage cells, the plurality of bit lines being subdivided into a plurality of groups of bit lines, each bit line group including at least one bit line, the semiconductor memory array comprising: for each bit line group, each bit line in said bit line group including switching means that responds to an inactive read/load signal by segmenting each said bit line into a plurality of electrically isolated bit line segments, each bit line segment having at least one data storage cell associated therewith, said switching means responding to an active read/load signal by electrically connecting each of said bit line segments; for each of said bit line segments in a bit line group, a data latch associated therewith, each data latch responding to an active strobe signal by loading data provided at inputs to said data latch; a plurality of input lines; and for each bit line group, column-select switching means connected between said plurality of input lines and said bit lines of said bit line group and that responds to an active column-select signal by electrically connecting said input lines to said bit lines such that data provided on said input lines is provided at the inputs of said data latches associated with said bit line group, whereby said data is loaded into said data latch of said bit line group having an active strobe signal applied thereto.

Claim 3

A method of storing data within a memory array formed in a silicon substrate, the array including a cell matrix defined by a plurality of rows and a plurality of columns of data storage cells, comprising the steps of: connecting bit line segments within a column in response to a read/load signal; loading data into a plurality of page latches; disconnecting each bit line segment within the column in response to the absence of said read/load signal; simultaneously transferring the data from each page latch to a respective set of data storage cells; and connecting bit line segments within each column in response to said read/load signal.

Claim 4

A method of storing data within a memory array formed in a silicon substrate, the array including a cell matrix defined by a plurality of rows and a plurality of columns of data storage cells, comprising the steps of: connecting bit line segments within a column in response to a read/load signal; loading data into a plurality of page latches; disconnecting each bit line segment within the column in response to the absence of said read/load signal; simultaneously transferring the data from each page latch to a respective set of data storage cells; and connecting bit line segments within each column in response to said read/load signal.