US5420539A
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Negative feedback CMOS differential amplifier operating in common mode
Assignee: STMicroelectronics SA
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Filing: 1994-06-02
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Granted: 1995-05-30
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Expires: 2014-06-02
Abstract
Abstract In a CMOS amplifier having a differential input and differential output, the input stage includes two legs, each of which includes an input transistor. A common mode negative feedback stage includes a load connected to the high supply voltage, a first transistor connected between the load and a common terminal of the input transistors. The first transistor is biased to the desired common mode voltage. A second transistor is connected between the load and the low supply voltage, and has a gate connected to a voltage corresponding to the mean voltage of the output stage. An additional transistor is disposed in parallel with each input transistor. Each additional transistor has its gate connected to the desired common mode voltage.
Inventors
- 👤 Thierry Fensch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:07
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F3/45188; H03F3/45479; H03F3/45632; H03F3/45636; H03F3/45641; H03F3/4565; H03F2203/00; H03F2203/45; H03F2203/45008; H03F2203/45024; H03F2203/45074; H03F2203/45082; H03F2203/45221; H03F2203/45371; H03F2203/45381; H03F2203/45418; H03F2203/45424; H03F2203/45466; H03F2203/45631; H03F2203/45711
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
59 words
A differential amplifier, comprising: a differential input stage having two circuit legs, each leg including an input device for receiving an input voltage and controlling a current through the device in response to the input voltage; a biasing circuit that maintains a flow of current through the circuit legs of the input stage when the input devices become non-conductive.
Claim 2
Dependent Claim
59 words
A differential amplifier, comprising: a differential input stage having two circuit legs, each leg including an input device for receiving an input voltage and controlling a current through the device in response to the input voltage; a biasing circuit that maintains a flow of current through the circuit legs of the input stage when the input devices become non-conductive.
Claim 3
Dependent Claim
13 words
The amplifier of claims 1, wherein the amplifier is of a CMOS type.
Claim 4
Dependent Claim
21 words
The amplifier of claim 1, wherein the bias circuit is coupled in parallel with at least one of the input devices.
Claim 5
Dependent Claim
19 words
The amplifier of claim 3, wherein the bias circuit is coupled in parallel with both of the input devices.
Claim 6
Dependent Claim
39 words
The amplifier of claim 4, wherein the bias circuit includes a transistor connected in parallel with each of the two input devices, each transistor having a control terminal coupled to a signal indicative of a desired common mode voltage.
Claim 7
Dependent Claim
18 words
The amplifier of claim 1, further comprising a common mode feedback circuit coupled to the differential input stage.
Claim 8
Dependent Claim
28 words
The amplifier of claim 6, wherein the common mode feedback circuit supplies a feedback current to the differential input stage that reduces the current through the input devices.
Claim 9
Dependent Claim
28 words
The amplifier of claim 7, wherein the feedback current increases with an increase in a difference between an actual common mode voltage and a desired common mode voltage.
Claim 10
Dependent Claim
52 words
The amplifier of claim 1, further comprising a differential output stage having two circuit legs, each leg providing an output voltage and being coupled to one of the input stage legs, wherein a gain between each output voltage and input voltage in a coupled pair of input and output legs is non-inverting.
Claim 11
Dependent Claim
76 words
The amplifier of claim 9, further including: a common mode circuit that receives the output voltages and generates a common mode voltage signal; and a common mode feedback circuit coupled to the differential input stage, that generates, in response to a difference between the common mode voltage signal and a signal indicative of a desired common mode voltage, a feedback signal that couples to the differential input stage to reduce the current through the input devices.
Claim 12
Dependent Claim
36 words
The amplifier of claim 10, wherein the biasing circuit comprises a transistor connected in parallel with each input device, each transistor having a control terminal coupled to the signal indicative of the desired common mode voltage.
Claim 13
Dependent Claim
13 words
The circuit of claim 11, wherein the amplifier is of a CMOS type.
Claim 14
Dependent Claim
107 words
A differential amplifier, comprising: first and second circuit branches having first and second currents, respectively, each branch including an input transistor for receiving an input voltage and controlling a transistor current in response to the input voltage, the first and second circuit branches being joined together at a common junction; a third circuit branch supplying a third current to the common junction, the first, second, and third currents summing together to form a substantially constant current; a bias circuit connected in parallel with the input transistors, that maintains the first and second currents above a predetermined threshold current when the transistor currents fall below the predetermined threshold.
Claim 15
Dependent Claim
107 words
A differential amplifier, comprising: first and second circuit branches having first and second currents, respectively, each branch including an input transistor for receiving an input voltage and controlling a transistor current in response to the input voltage, the first and second circuit branches being joined together at a common junction; a third circuit branch supplying a third current to the common junction, the first, second, and third currents summing together to form a substantially constant current; a bias circuit connected in parallel with the input transistors, that maintains the first and second currents above a predetermined threshold current when the transistor currents fall below the predetermined threshold.
Claim 16
Dependent Claim
25 words
The amplifier of claim 13, wherein the third current is supplied by a common mode feedback circuit that receives a common mode signal as input.
Claim 17
Dependent Claim
35 words
The amplifier of claim 14, wherein the bias circuit comprises a bias transistor connected in parallel with each of the input transistors, each bias transistor having a control terminal coupled to the common mode signal.
Claim 18
Dependent Claim
57 words
A differential amplifier, comprising: a differential input stage having two circuit legs, each leg including a device for receiving an input voltage and controlling a current through the device in response to the input voltage; bias means for maintaining a flow of current through the circuit legs of the input stage when the input devices become non-conductive.
Claim 19
Dependent Claim
57 words
A differential amplifier, comprising: a differential input stage having two circuit legs, each leg including a device for receiving an input voltage and controlling a current through the device in response to the input voltage; bias means for maintaining a flow of current through the circuit legs of the input stage when the input devices become non-conductive.
Claim 20
Dependent Claim
19 words
The amplifier of claim 16, further including means, coupled to the input stage, for generating a differential output voltage.
Claim 21
Dependent Claim
39 words
The amplifier of claim 17, wherein the differential output voltage has a common mode voltage, and further including feedback means, responsive to the common mode voltage, for generating a common mode feedback signal coupled to the differential input stage.
Claim 22
Dependent Claim
21 words
The amplifier of claim 18, wherein the feedback means includes means for varying the current through the first and second devices.
Claim 23
Dependent Claim
40 words
The amplifier of claim 16, wherein the bias means includes means for shunting current around the input devices to maintain a flow of current though the first and second legs of the input stage when the input devices become non-conductive.
Claim 24
Dependent Claim
75 words
The amplifier of claim 20, further including: means for generating a signal indicative of a desired common mode output voltage; and means for activating the bias means when both input voltages cross the signal indicative of the desired common mode output voltage in a first direction, and for deactivating the bias means when at least one of the input voltages crosses the signal indicative of the desired common mode output voltage in a second direction.
Claim 25
Independent Claim
93 words
A method for maintaining a flow of current in an input stage of a differential amplifier having a pair of input devices, comprising the steps of: generating a threshold signal indicative of an input voltage to the differential amplifier for which the pair of input devices are conductive; shunting current around the input devices when both input voltages cross the threshold signal in a first direction, and substantially terminating the shunting of current when at least one of the input voltages crosses the threshold signal in a second direction opposite the first direction.
Claim 26
Independent Claim
93 words
A method for maintaining a flow of current in an input stage of a differential amplifier having a pair of input devices, comprising the steps of: generating a threshold signal indicative of an input voltage to the differential amplifier for which the pair of input devices are conductive; shunting current around the input devices when both input voltages cross the threshold signal in a first direction, and substantially terminating the shunting of current when at least one of the input voltages crosses the threshold signal in a second direction opposite the first direction.
References Cited (Backward Citations)
US5319316A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |