Linear bipolar junction transistor amplifier

Claim 2

A linear amplifier comprising: a first differential pair having first and second bipolar transistors; a second differential pair having third and fourth bipolar transistors; a third differential pair having fifth and sixth bipolar transistors; first, second and third constant current sources, said first current source connected to commonly connected emitters of said first and second transistors, said second current source connected to commonly connected emitters of said third and fourth transistors, said third current source connected to commonly connected emitters of said fifth and sixth transistors, respective bases of said first, third and fifth transistors connected to a first input; respective bases of said second, fourth and sixth transistors connected to a second input, respective collectors of said first, third and fifth transistors connected to a first output, respective collectors of said second, fourth and sixth transistors connected to a second output, said first and second outputs being connected to a positive supply via first and second load resistors respectively, wherein the gain of said amplifier is linearized by an offset voltage generated by ratioed bipolar transistors, the ratio being an integer greater than four.

Claim 3

A linear amplifier as defined in claim 1, said ratioed transistors being in two of said first, second or third differential pairs.

Claim 4

A linear amplifier as defined in claim 1, said ratioed transistors being in said first and second differential pairs wherein the effective emitter area of said first transistor is larger than the effective emitter area of the second transistor by a factor N and the effective emitter area of the third transistor is smaller than the effective emitter area of the fourth transistor by a factor N, N being an integer.

Claim 5

A linear amplifier as defined in claim 3, wherein N=9.

Claim 6

A linear amplifier as defined in claim 1, said first and second outputs connected to first and second cascode output stages respectively.

Claim 7

A linear amplifier as defined in claim 1, said first, second and third current sources being matched.

Claim 8

A linear amplifier comprising: a first differential pair having first and second bipolar transistors; a second differential pair having third and fourth bipolar transistors; a third differential pair having fifth and sixth bipolar transistors; first, second and third constant current sources, said first current source connected to commonly connected emitters of said first and second transistors, said second current source connected to commonly connected emitters of said third and fourth transistors, said third current source connected to commonly connected emitters of said fifth and sixth transistors, respective bases of said first, third and fifth transistors selectively connected to a first input via a first emitter follower circuit; respective bases of said second, fourth and sixth transistors selectively connected to a second input via a second emitter follower circuit, respective collectors of said first, third and fifth transistors connected to a first output, respective collectors of said second, fourth and sixth transistors connected to a second output, said first and second outputs being connected to a positive supply via first and second load resistors respectively, wherein the gain of said amplifier is linearized by an offset voltage generated by ratioed bipolar transistors, the ratio being an integer.

Claim 9

A linear amplifier comprising: a first differential pair having first and second bipolar transistors; a second differential pair having third and fourth bipolar transistors; a third differential pair having fifth and sixth bipolar transistors; first, second and third constant current sources, said first current source connected to commonly connected emitters of said first and second transistors, said second current source connected to commonly connected emitters of said third and fourth transistors, said third current source connected to commonly connected emitters of said fifth and sixth transistors, respective bases of said first, third and fifth transistors selectively connected to a first input via a first emitter follower circuit; respective bases of said second, fourth and sixth transistors selectively connected to a second input via a second emitter follower circuit, respective collectors of said first, third and fifth transistors connected to a first output, respective collectors of said second, fourth and sixth transistors connected to a second output, said first and second outputs being connected to a positive supply via first and second load resistors respectively, wherein the gain of said amplifier is linearized by an offset voltage generated by ratioed bipolar transistors, the ratio being an integer.

Claim 10

A linear amplifier as defined in claim 7, said ratioed transistors being in said first and second emitter follower circuits.

Claim 11

A linear amplifier as defined in claim 8, said first emitter follower circuit comprising seventh and eighth input bipolar transistors and current sources comprising ninth and tenth bipolar transistors, the bases of the seventh and eighth transistors being commonly connected to an input terminal, respective collectors connected to the positive supply, the emitter of the seventh transistor connected to the base of the first transistor and the collector of the ninth transistor, the emitter of the eighth transistor connected to the bases of the third and fifth transistors, and the collector of the tenth transistor, the effective emitter area of the seventh transistor being smaller than the effective emitter area of the ninth transistor by a factor N and the effective emitter area of the eighth transistor being larger than the effective emitter area of the tenth transistor by a factor N, and said second emitter follower circuit comprises an eleventh and a twelfth input bipolar transistor and associated current sources comprising thirteenth and fourteenth bipolar transistors, the bases of said eleventh and twelfth transistors being commonly connected to an input terminal, respective collectors commonly connected to the positive supply, the emitter of the eleventh transistor connected to the base of the fourth transistor and the collector of the thirteenth transistor, the emitter of the twelfth transistor connected to the bases of the second and sixth transistors and the collector of the fourteenth transistor, the effective emitter area of the eleventh transistor being smaller than the effective emitter area of the thirteenth transistor by a factor N, and the effective emitter area of the twelfth transistor being larger than the effective emitter area of the fourteenth transistor by a factor N wherein N is an integer.

Claim 12

A linear amplifier as defined in claim 9 wherein N=3.