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US5410274A Expired / Lapsed US ⏱️ 0.0 years remaining

Single-ended and differential amplifiers with high feedback input impedance and low distortion

Assignee: Microelectronics Technology Inc
•
Filing: 1994-03-17
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Granted: 1995-04-25
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Expires: 2014-03-17
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Abstract

Abstract First and second current feedback transconductance amplifiers (102,104) each have a high impedance voltage input, a low impedance current input and a pair of push-pull current outputs. In a single-ended configuration, an input signal is applied to the voltage input of the first transconductance amplifier (102) and the push-pull outputs of the both transconductance amplifiers are connected through a current mirror (136,138) to a node (134) where the current outputs are summed. The node current is integrated by a capacitor (174) to produce a voltage which is amplified by a transimpedance amplifier (190) to produce an output voltage which is fed back to the voltage input of the second transconductance amplifier (104). The current inputs of the transconductance amplifiers (102,104) are interconnected by a resistor (132). The high impedance voltage inputs produce common-mode cancellation of distortion in the transconductance amplifiers (102,104) and low input shot noise. In a differential configuration, differential input signals are applied to the voltage inputs of transconductance amplifiers (260,262), and a separate transimpedance amplifier (292,316) and current mirror (278,280) (302,304) is provided for each transconductance amplifier (260,262). A common-mode feedback circuit (352) controls the common-mode output voltages of the transimpedance amplifiers (292,316) to ground. Switch means (402,404,406,408,410,412) may be added to selectively ground the voltage inputs of the transconductance amplifiers (260,262) and disable their input stages by disconnecting their power supplies (VCC,VEE).

Inventors

  • 👤 Dwight D. Birdsall
  • 👤 Phillip L. Elliott
  • 👤 Lloyd F. Linder
  • 👤 Kelvin T. Tran
  • 👤 Donald G. McMullin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 08:23
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3081; H03F3/26; H03F3/3066; H03F3/3067

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 124 words
A differential amplifier, comprising: first and second current feedback amplifier means, operable to produce first and second current outputs, said first and said second current outputs being summed together within a feedback loop, each including: a high impedance voltage input for receiving a differential input signal; a low impedance current input; and a voltage output for producing an output signal said voltage output operable to be fed back into the voltage input of said second feedback amplifier means thereby producing the feedback loop, said voltage output produced from the summation of said first and said second current outputs of said first and said second current feedback amplifier means; and resistance means interconnecting said current inputs of the first and second current feedback amplifier means.
Claim 2
Dependent Claim 124 words
A differential amplifier, comprising: first and second current feedback amplifier means, operable to produce first and second current outputs, said first and said second current outputs being summed together within a feedback loop, each including: a high impedance voltage input for receiving a differential input signal; a low impedance current input; and a voltage output for producing an output signal said voltage output operable to be fed back into the voltage input of said second feedback amplifier means thereby producing the feedback loop, said voltage output produced from the summation of said first and said second current outputs of said first and said second current feedback amplifier means; and resistance means interconnecting said current inputs of the first and second current feedback amplifier means.

References Cited (Backward Citations)

US4502020A Cited
US4780689A Cited
US4910477A Cited
US5045803A Cited
US4970470A Cited
US5097223A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-24 1998-10-24 1999-04-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-04-24 2002-10-24 2003-04-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-04-24 2006-10-24 2007-04-25 $7700.00 Window Closed / Lapsed

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