US5409865A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for assembling a TAB grid array package for an integrated circuit
Assignee: UTAC Hong Kong Ltd
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Filing: 1994-02-25
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Granted: 1995-04-25
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Expires: 2014-02-25
Abstract
Abstract A TAB Grid Array (TGA) package is a package for an integrated circuit. A TGA package provides an efficient structure and method to connect a semiconductor die encapsulated in the TGA package to an external printed circuit board (PCB). The TGA package uses a tape automated bonding (TAB) technique to provide a generally flexible dielectric film bearing a pattern of conductive traces radially emanating from a die aperture to connect to an area array of pads arranged on the tape perimeter. The pads of area array of pads are connected to the TAB traces using conventional TAB inner lead bonding techniques, or alternatively, wire bonding methods, with both the semiconductor die and the TAB traces facing down towards the PCB. In one embodiment, the back of a semiconductor die and the TAB tape are attached to a stiffener via suitable bonding agents. The stiffener provides the mechanical rigidity to the package and efficiently removes the dissipated power. By using an encapsulation material, both the semiconductor die and the bonds between the semiconductor die and the TAB tape are protected from the environment. Solder balls are attached on the area array of pads of the TGA package facing down. These same solder balls in turn are used to electrically and mechanically connect the package to the external PCB.
Inventors
- 👤 Marcos Karnezos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:43
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W70/00; H10W70/40; H10W70/453; H10W70/60; H10W70/611; H10W70/614; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W72/701; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
An assembly process for fabricating an integrated circuit package, comprising the steps: bonding electrically conductive traces on a TAB tape to corresponding conductive pads of a semiconductor die using inner lead bonds, said conductive traces of said TAB tape being held between a first and a second dielectric layer; attaching said semiconductor die to the back wall of a cavity in a heat spreader using a thermally conductive adhesive; attaching said TAB tape to said heat spreader using a TAB adhesive; curing said thermally conductive adhesive and said TAB adhesive; encapsulating said die and said inner lead bonds by filling said cavity with an encapsulation material and covering said semiconductor die and said inner lead bonds leaving no voids; curing the encapsulating material; applying solder flux on one or more solder balls; attaching solder balls to conductive pads of said TAB tape; reflowing said solder balls by applying heat; cleaning excess flux from said conductive pads using an appropriate cleaning agent; and dry baking said integrated circuit package.
Claim 2
Dependent Claim
168 words
An assembly process for fabricating an integrated circuit package, comprising the steps: bonding electrically conductive traces on a TAB tape to corresponding conductive pads of a semiconductor die using inner lead bonds, said conductive traces of said TAB tape being held between a first and a second dielectric layer; attaching said semiconductor die to the back wall of a cavity in a heat spreader using a thermally conductive adhesive; attaching said TAB tape to said heat spreader using a TAB adhesive; curing said thermally conductive adhesive and said TAB adhesive; encapsulating said die and said inner lead bonds by filling said cavity with an encapsulation material and covering said semiconductor die and said inner lead bonds leaving no voids; curing the encapsulating material; applying solder flux on one or more solder balls; attaching solder balls to conductive pads of said TAB tape; reflowing said solder balls by applying heat; cleaning excess flux from said conductive pads using an appropriate cleaning agent; and dry baking said integrated circuit package.
Claim 3
Dependent Claim
13 words
A process as in claim 1, wherein said bonding step uses thermosonic bonding.
Claim 4
Dependent Claim
15 words
A process as in claim 1, wherein said bonding step uses bumpless inner lead bonding.
Claim 5
Dependent Claim
17 words
A process as in claim 1, wherein said encapsulating step is performed using a syringe-dispensed encapsulation material.
Claim 6
Dependent Claim
173 words
An assembly process for fabricating an integrated circuit package, comprising the steps: attaching a TAB tape to a heat spreader using a TAB adhesive, said heat spreader having a cavity for accommodating a semiconductor die; attaching a semiconductor die to the back wall of said cavity in said heat spreader using a thermally conductive adhesive; curing said thermally conductive adhesive and said TAB adhesive; bonding said heat spreader and electrically conductive traces on a TAB tape to corresponding conductive pads of a semiconductor die using wire bonds, said conductive traces of said TAB tape being held between a first and a second dielectric layer; encapsulating said die by filling said cavity with an encapsulation material and covering said semiconductor die leaving no voids; curing the encapsulating material; applying solder flux on one or more solder balls; attaching said solder balls to conductive pads on said TAB tape; reflowing said solder balls by applying heat; cleaning excess flux from said conductive pads using an appropriate cleaning agent; and dry baking said integrated circuit package.
Claim 7
Dependent Claim
173 words
An assembly process for fabricating an integrated circuit package, comprising the steps: attaching a TAB tape to a heat spreader using a TAB adhesive, said heat spreader having a cavity for accommodating a semiconductor die; attaching a semiconductor die to the back wall of said cavity in said heat spreader using a thermally conductive adhesive; curing said thermally conductive adhesive and said TAB adhesive; bonding said heat spreader and electrically conductive traces on a TAB tape to corresponding conductive pads of a semiconductor die using wire bonds, said conductive traces of said TAB tape being held between a first and a second dielectric layer; encapsulating said die by filling said cavity with an encapsulation material and covering said semiconductor die leaving no voids; curing the encapsulating material; applying solder flux on one or more solder balls; attaching said solder balls to conductive pads on said TAB tape; reflowing said solder balls by applying heat; cleaning excess flux from said conductive pads using an appropriate cleaning agent; and dry baking said integrated circuit package.
Claim 8
Dependent Claim
17 words
A process as in claim 5, wherein said encapsulating step is performed using a syringe-dispensed encapsulation material.
Claim 9
Dependent Claim
24 words
A process as in claim 6, wherein said encapsulation material is cured for three hours during which the temperature is ramped at three steps.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-24 | 1998-10-24 | 1999-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-24 | 2002-10-24 | 2003-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-24 | 2006-10-24 | 2007-04-25 | $7700.00 | Window Closed / Lapsed |