System and Method for booting computer for operation in either of two byte-order modes

Claim 1

A computer system capable of operating in either a first byte-order mode for processing information characterized by a first byte order or a second byte-order mode for processing information characterized by a second byte order, comprising: means for specifying a desired one of the first and second byte-order modes, said means for specifying having a default condition at power-on that specifies the first byte-order mode; a CPU that is configurable on reset for operation in either of the first and second byte-order modes in response to said means for specifying; a first non-volatile memory having stored therein a first set of information including a first program, said first set of information being characterized by the first byte order; a second non-volatile memory having stored therein a second set of information including a second program and a data item, said data item indicating the first byte-order mode if said second set of information is characterized by the first byte order and the second byte-order mode if said second set of information is characterized by the second byte order; and an address mapping circuit coupled to said first and second non-volatile memories, operable to provide a selected one of first and second address mappings; said first address mapping having said first set of information accessible starting at a startup address and said second set of information accessible at an address having a displacement from said startup address; said second address mapping having said second set of information accessible at said startup address; said address mapping circuit providing said first address mapping as a default at power-on so that said CPU executes said first program at power-on; said first program, when executed, causing the following actions to occur reading said data item in said second set of information to determine which byte-order mode is indicated, if and only if said data item indicates the second byte-order mode, causing said means for specifying to specify the second byte-order mode, effective only on reset, causing said address mapping circuit to provide said second address mapping, effective only on reset, and initiating a reset of said CPU; whereby when said CPU is reset, said second set of information is mapped to said startup address, said means for specifying configures said CPU for operation in the byte-order mode indicated by said data item, and execution of said second program commences with said CPU configured to operate in a byte-order mode that is consistent with the byte order that characterizes said second set of information.