US5408606A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer graphics system with parallel processing using a switch structure
Assignee: Evans and Sutherland Computer Corp
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Filing: 1993-01-07
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Granted: 1995-04-18
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Expires: 2013-01-07
Abstract
Abstract Front end processors in a graphics architecture execute parallel scan conversion and shading to first process individually assigned primitive objects for providing update pixels. A crossbar accommodates data rearrangement whereby parallel pixel processors with associated memory capabilities (frame buffer banks) perform visibility and blending operations on predetermined sequences of update pixels to provide display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines or distributed over an area. Specific distribution criteria are disclosed for patterns. One form of pixel processor organization incorporates a distributed frame buffer with FIFO memory and control stacks. Display pixels are received by a multiplexer to supply a digital-analog connector with display data in raster sequence.
Inventors
- 👤 Glen A. Eckart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:51
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
141 words
A graphics system for processing primitive data, as from a host computer, to provide display data in the form of display pixels related to locations in a display, said graphics system comprising: a structure for processing said primitive data to provide representative update pixels related to the locations in said display; a plurality of visibility-and-blend processors, said visibility-and-blend processors each including an associated frame buffer bank, the frame buffer banks collectively defining a composite frame buffer, each frame buffer bank for storing predetermined frame buffer pixels that are spaced apart and in sequence skipping locations of said display, said plurality of visibility-and-blend processors each for iteratively processing said update pixels in said associated frame buffer bank; and a switch structure for supplying said update pixels to said plurality of visibility-and-blend processors in accordance with said sequence skipping locations of said display.
Claim 2
Dependent Claim
141 words
A graphics system for processing primitive data, as from a host computer, to provide display data in the form of display pixels related to locations in a display, said graphics system comprising: a structure for processing said primitive data to provide representative update pixels related to the locations in said display; a plurality of visibility-and-blend processors, said visibility-and-blend processors each including an associated frame buffer bank, the frame buffer banks collectively defining a composite frame buffer, each frame buffer bank for storing predetermined frame buffer pixels that are spaced apart and in sequence skipping locations of said display, said plurality of visibility-and-blend processors each for iteratively processing said update pixels in said associated frame buffer bank; and a switch structure for supplying said update pixels to said plurality of visibility-and-blend processors in accordance with said sequence skipping locations of said display.
Claim 3
Dependent Claim
31 words
A system according to claim 1 wherein said structure for processing said primitive data comprises a plurality of primitive processors for iteratively receiving and processing the primitive data for individual primitives.
Claim 4
Dependent Claim
24 words
A system according to claim 2 wherein said primitive processors receive primitive coherent data, said plurality of visibility-and-blend processors receive screen space coherent data.
Claim 5
Dependent Claim
17 words
A system according to claim 3 further including a display unit coupled to receive display sequence data.
Claim 6
Dependent Claim
35 words
A system according to claim 3 further including a pixel multiplexer for receiving frame buffer pixels from said frame buffer banks to provide said display pixels in a display sequence according to a raster pattern.
Claim 7
Dependent Claim
22 words
A system according to claim 1 wherein said structure for processing said primitive data includes means for scan converting said primitive data.
Claim 8
Dependent Claim
22 words
A system according to claim 6 wherein said structure for processing said primitive data further includes means for shading said primitive data.
Claim 9
Dependent Claim
29 words
A system according to claim 1 wherein said plurality of visibility-and-blend processors determine visibility between said update pixels and content of said associated frame buffer bank to resolve contention.
Claim 10
Dependent Claim
19 words
A system according to claim 1 wherein said plurality of visibility-and-blend processors further include FIFOs for storing pixel data.
Claim 11
Dependent Claim
30 words
A system according to claim 1 further including a display pixel multiplexer for receiving display pixels from said frame buffer banks to provide said display pixels in a display sequence.
Claim 12
Dependent Claim
14 words
A system according to claim 10 wherein said display sequence is a raster pattern.
Claim 13
Dependent Claim
18 words
A system according to claim 1 wherein said sequence skipping locations are related to a raster scan pattern.
Claim 14
Dependent Claim
23 words
A system according to claim 1 wherein said sequence skipping locations are specified in line raster numerical sequence with skip voids between lines.
Claim 15
Dependent Claim
56 words
A system according to claim 13 wherein said frame buffer pixels are addressed to said frame buffer banks in accordance with the following: address of frame buffer bank as related to a numerical sequence raster scan=(y·X SC +x) mod n where: y=raster line, x=pixel in line, X SC =length of scan line, and n=number of banks
Claim 16
Dependent Claim
56 words
A system according to claim 13 wherein said frame buffer pixels are addressed to said frame buffer banks in accordance with the following: address in said frame buffer banks as related to a numerical sequence raster scan=(y·X SC +x)div n where: y=raster line, x=pixel in line, X SC =length of scan line, and n=number of banks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |