Abstract Ultra-small equal-width lines and spaces are generated on an integrated circuit wafer using multiple exposures and phase-shifting at the wafer level. In particular, an integrated circuit wafer is coated with a layer of photoresist and then masked using a mask defining a pattern of multiple feature lines arranged at a regular line pitch. The layer of photoresist is then underexposed so as to partially bleach portions of the layer of photoresist in accordance with the pattern. Next, the mask and the integrated circuit wafer are positionally translated relative to one another by a predetermined fraction of the line pitch, and the layer of photoresist is then again underexposed. Developing the photoresist layer creates a stepped profile. The layer of photoresist is then blanket exposed, the stepped profile causing exposure in the vicinity of steps to be retarded. The layer of photoresist is then developed, producing thin lines of photoresist separated by substantially equal spaces of no photoresist.
A method of producing feature lines in a layer of photoresist on an integrated circuit wafer, comprising the steps of: coating the integrated circuit wafer with a layer of photoresist; masking the photoresist layer using a mask defining a pattern of multiple features lines arranged at a regular line pitch; through said mask, under-exposing the layer of photoresist so as to partially bleach portions of the layer of photoresist in accordance with said pattern; positionally translating the mask and integrated circuit wafer relative to one another, in a direction in which the line pitch is measured, by a pre-determined fraction of the line pitch; again under-exposing the layer of photoresist through said mask; developing the layer of photoresist, creating a stepped profile; blanket exposing the layer of photoresist; and developing the layer of photoresist.
Claim 2
Independent Claim
134 words
A method of producing feature lines in a layer of photoresist on an integrated circuit wafer, comprising the steps of: coating the integrated circuit wafer with a layer of photoresist; masking the photoresist layer using a mask defining a pattern of multiple features lines arranged at a regular line pitch; through said mask, under-exposing the layer of photoresist so as to partially bleach portions of the layer of photoresist in accordance with said pattern; positionally translating the mask and integrated circuit wafer relative to one another, in a direction in which the line pitch is measured, by a pre-determined fraction of the line pitch; again under-exposing the layer of photoresist through said mask; developing the layer of photoresist, creating a stepped profile; blanket exposing the layer of photoresist; and developing the layer of photoresist.