Elevator control apparatus with compensation for current sensor offset voltage

Claim 2

An elevator control apparatus comprising: a converter for converting AC power into DC power; an inverter for converting the DC power resulting from the conversion by said converter into AC voltage of a variable voltage and a variable frequency so as to drive with the AC voltage an induction motor for vertically moving a car of said elevator; a current detector for detecting the current output by said inverter and for producing an output signal indicative of the detected current; a current command generating circuit for generating a current command value for said induction motor; a control circuit for controlling said inverter on the basis of both the current command value from said current command generating circuit and the output signal from said current detector; and a cancellation circuit for cancelling offset voltage by storing, when said inverter is stopped while said current command generating circuit keeps generating the current command value, the output signal of said current detector, and by adding, when the inverter is in operation, the stored output signal to the present output signal of said current detector.

Claim 3

A control apparatus according to claim 1 further comprising an inverter stoppage signal generating circuit for generating, on the basis of a car speed command, a stoppage signal for commanding said control circuit to bring said inverter to stoppage.

Claim 4

A control apparatus according to claim 2 wherein said cancellation circuit includes an amplifier for amplifying the output signal of said current detector with a predetermined gain, a sample-and-hold circuit for sampling outputs of said amplifier, and a capacitor for maintaining a value sampled by said sample-and-hold circuit.

Claim 5

A control apparatus according to claim 3 wherein said sample-and-hold circuit is in its sampling state when supplied with the stoppage signal generated from said inverter stoppage signal generating circuit, and is in its holding state when not supplied with the stoppage signal.

Claim 6

A control apparatus according to claim 1 wherein said inverter outputs three-phase AC current of U-phase, V-phase and W-phase, said current detector comprising a U-phase detector and a V-phase detector for respectively detecting the U-phase current and V-phase current from said inverter, said cancellation circuit comprising a U-phase cancellation circuit for inputting the output of said U-phase detector, a V-phase cancellation circuit for inputting the output of said V-phase detector, and a W-phase cancellation circuit for adding together the outputs of said U-phase and V-phase cancellation circuits.

Claim 7

An elevator control apparatus comprising: a converter for converting AC power into DC power; an inverter for converting the DC power into AC voltage having a variable voltage and a variable frequency so as to drive an induction motor with the AC voltage; a first phase current detector for detecting a first phase of the current output by said inverter and for producing an output signal indicative of the first phase of the detected current; a second phase current detector for detecting a second phase of the current output by said inverter and for producing an output signal indicative of the second phase of the detected current; a current command generating circuit for generating a current command value for the induction motor; a control circuit for controlling said inverter on the basis of both the current command value generated by said current command generating circuit and the output signal produced by said first and second current detectors; means for generating an inverter stoppage signal; a first phase cancellation circuit connected to said first phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a second phase cancellation circuit connected to said second phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a third phase cancellation circuit connected to said first and second phase cancellation circuits, said third phase cancellation circuit comprising a differential amplifier; wherein said first phase cancellation circuit produces a signal indicative of a first phase offset voltage, said second phase cancellation circuit produces a signal indicative of a second phase offset voltage and said third phase cancellation circuit produces a signal indicative of the sum of the first and second phase offset voltages.

Claim 8

An elevator control apparatus comprising: a converter for converting AC power into DC power; an inverter for converting the DC power into AC voltage having a variable voltage and a variable frequency so as to drive an induction motor with the AC voltage; a first phase current detector for detecting a first phase of the current output by said inverter and for producing an output signal indicative of the first phase of the detected current; a second phase current detector for detecting a second phase of the current output by said inverter and for producing an output signal indicative of the second phase of the detected current; a current command generating circuit for generating a current command value for the induction motor; a control circuit for controlling said inverter on the basis of both the current command value generated by said current command generating circuit and the output signal produced by said first and second current detectors; means for generating an inverter stoppage signal; a first phase cancellation circuit connected to said first phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a second phase cancellation circuit connected to said second phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a third phase cancellation circuit connected to said first and second phase cancellation circuits, said third phase cancellation circuit comprising a differential amplifier; wherein said first phase cancellation circuit produces a signal indicative of a first phase offset voltage, said second phase cancellation circuit produces a signal indicative of a second phase offset voltage and said third phase cancellation circuit produces a signal indicative of the sum of the first and second phase offset voltages.

Claim 9

An offset voltage cancellation circuit for an inverter comprising: a first phase current detector connected to a first phase output of the inverter; a second phase current detector connected to a second phase output of the inverter; a first phase cancellation circuit connected to said first phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a second phase cancellation circuit connected to said second phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a third phase cancellation circuit connected to said first and second phase cancellation circuits, said third phase cancellation circuit comprising a differential amplifier; and means for generating an inverter stoppage signal connected to the sample and hold circuits of said first phase cancellation circuit and said second phase cancellation circuit, respectively; whereby said first phase cancellation circuit produces a signal indicative of a first phase offset voltage, said second phase cancellation circuit produces a signal indicative of a second phase offset voltage and said third phase cancellation circuit produces a signal indicative of the sum of the first and second phase offset voltages.

Claim 10

An offset voltage cancellation circuit for an inverter comprising: a first phase current detector connected to a first phase output of the inverter; a second phase current detector connected to a second phase output of the inverter; a first phase cancellation circuit connected to said first phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a second phase cancellation circuit connected to said second phase current detector comprising an amplifier having an output connected to a sample and hold circuit; a third phase cancellation circuit connected to said first and second phase cancellation circuits, said third phase cancellation circuit comprising a differential amplifier; and means for generating an inverter stoppage signal connected to the sample and hold circuits of said first phase cancellation circuit and said second phase cancellation circuit, respectively; whereby said first phase cancellation circuit produces a signal indicative of a first phase offset voltage, said second phase cancellation circuit produces a signal indicative of a second phase offset voltage and said third phase cancellation circuit produces a signal indicative of the sum of the first and second phase offset voltages.