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US5406630A Expired / Lapsed US ⏱️ 0.0 years remaining

Tamperproof arrangement for an integrated circuit device

Assignee: Motorola Solutions Inc
•
Filing: 1994-01-10
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Granted: 1995-04-11
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Expires: 2014-01-10
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Abstract

Abstract A tamperproof arrangement for an integrated circuit device. The arrangement includes a package and lid fabricated of heavy metals to prevent X-radiation or infrared detection of circuit operation. Sensors and control circuitry are located on the integrated circuit die itself which detect increased temperature and radiation and clear or zeroize any sensitive information included within the integrated circuit device. Electrode finger grids above and below the integrated circuit die detect physical attempts to penetrate the integrated circuit die. Critical circuit functions are segregated from non-critical functions. Power applied to the integrated circuit device is monitored and separated for critical and non-critical circuit functions.

Inventors

  • 👤 Gerald V. Piosenka
  • 👤 David M. Harrison
  • 👤 Ronald V. Chandos

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 14:20
CPC Classifications
H; H10; H10D; H10D89/00; G; G01; G01K; G01K7/00; G01K7/01; G08; G08B; G08B13/00; G08B13/02; G08B13/12; G08B13/126; G08B13/128; H10W; H10W40/00; H10W42/00; H10W42/20; H10W42/40; H10W42/405; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/5453; H10W72/547; H10W72/5473; H10W74/00; H10W76/00; H10W76/60; H10W90/00; H10W90/701; H10W90/751; H10W90/756

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 106 words
A tamperproof method for an integrated circuit die comprising the steps of: segregating critical circuit functions from non-critical circuit functions on said integrated circuit die; locating said critical circuit functions substantially in the center of the integrated circuit die; providing temperature sensors in said critical circuit area of said integrated circuit die to detect excessive temperature; providing radiation sensors in said critical circuit area of said integrated circuit die to detect excessive radiation levels in said critical circuit area; and clearing all memory elements in said critical circuit function area, if excessive temperature or excessive radiation is detected by said temperature sensors or radiation sensors respectively.
Claim 2
Dependent Claim 106 words
A tamperproof method for an integrated circuit die comprising the steps of: segregating critical circuit functions from non-critical circuit functions on said integrated circuit die; locating said critical circuit functions substantially in the center of the integrated circuit die; providing temperature sensors in said critical circuit area of said integrated circuit die to detect excessive temperature; providing radiation sensors in said critical circuit area of said integrated circuit die to detect excessive radiation levels in said critical circuit area; and clearing all memory elements in said critical circuit function area, if excessive temperature or excessive radiation is detected by said temperature sensors or radiation sensors respectively.
Claim 3
Dependent Claim 33 words
A tamperproofing method as claimed in claim 1, wherein there is further included the step of separating power and ground leads for said non-critical circuit function area and said critical circuit function area.

References Cited (Backward Citations)

US4734883A Cited
US4691350A Cited
US4860351A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-10 1998-10-10 1999-04-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-04-10 2002-10-10 2003-04-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-04-10 2006-10-10 2007-04-11 $7700.00 Window Closed / Lapsed

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