US5406607A
Expired / Lapsed
US
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Apparatus, systems and methods for addressing electronic memories
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-02-24
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Granted: 1995-04-11
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Expires: 2014-02-24
Abstract
Abstract A circuit is disclosed for reducing the number of signal lines passing through a connector (205) comprised of a shift register coupled to a plurality of input data lines and half as many output data lines. When a load signal is received, the shift register latches the data from the input data lines and immediately transmits half of the data to the output data lines and through the connector. When the shift register receives a shift signal, the other half of the data is shifted onto the same output lines and pass through the connector to achieve a two-to-one multiplexing function.
Inventors
- 👤 Bryan D. Marietta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:55
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1657
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
122 words
A circuit for reducing the number of signal lines passing through a connector comprising: a plurality of input data signal lines; at least one output data signal line connected to said connector; a shift signal line; a load signal line; and a shift register having a plurality of data inputs, a plurality of data outputs, a shift input and a load input wherein at least two of said data inputs are coupled to at least two of said input data signal lines, at least one of said data outputs is coupled to at least one of said output data signal lines, said shift input is coupled to said shift signal line and said load input is coupled to said load signal line.
Claim 2
Dependent Claim
122 words
A circuit for reducing the number of signal lines passing through a connector comprising: a plurality of input data signal lines; at least one output data signal line connected to said connector; a shift signal line; a load signal line; and a shift register having a plurality of data inputs, a plurality of data outputs, a shift input and a load input wherein at least two of said data inputs are coupled to at least two of said input data signal lines, at least one of said data outputs is coupled to at least one of said output data signal lines, said shift input is coupled to said shift signal line and said load input is coupled to said load signal line.
Claim 3
Dependent Claim
49 words
The circuit in claim 1 wherein a first of said data inputs receives a first bit of data from a first of said input data signal lines and a second of said data inputs receives a second bit of data from a second of said input data signal lines.
Claim 4
Dependent Claim
61 words
The circuit in claim 2 wherein said shift register transmits said first data bit from said first data input to a first of said data outputs and transmits said second data bit from said second data input to a second of said data outputs whenever said shift register receives a load signal from said load signal line on said load input.
Claim 5
Dependent Claim
41 words
The circuit in claim 3 wherein said shift register transmits said first data bit from said first data output to said second data output whenever said shift register receives a shift signal from said shift signal line on said shift input.
Claim 6
Dependent Claim
18 words
The circuit in claim 4 wherein said second data output is coupled to said output data signal line.
Claim 7
Dependent Claim
45 words
The circuit in claim 3 including a serial input signal line and wherein said shift register receives a serial input data bit from said serial input signal line on a serial input of said shift register which is coupled to said serial input signal line.
Claim 8
Dependent Claim
61 words
The circuit in claim 6 wherein said shift register transmits said first data bit from said first data output to said second data output and transmits said serial input data bit from said serial input of said shift register to said first data output whenever said shift register receives a shift signal from said shift signal line on said shift input.
Claim 9
Dependent Claim
18 words
The circuit in claim 7 wherein said first data output is coupled to said output data signal line.
Claim 10
Dependent Claim
35 words
The circuit in claim 7 wherein said shift register is called a "first shift register" and including a second shift register having a data output coupled to said serial input of said first shift register.
Claim 11
Dependent Claim
118 words
A circuit for reducing the number of signal lines passing through a connector comprising: eight input data signal lines; four output data signal lines connected to said connector; a shift signal line; a load signal line; and a shift register having eight data inputs, eight data outputs, a shift input, and a load input, wherein at least two of said eight data inputs are coupled to at least two of said eight input data signal lines, at least one of said eight data outputs is coupled to at least one of said four output data signal lines, said shift input is coupled to said shift signal line and said load input is coupled to said load signal line.
Claim 12
Dependent Claim
118 words
A circuit for reducing the number of signal lines passing through a connector comprising: eight input data signal lines; four output data signal lines connected to said connector; a shift signal line; a load signal line; and a shift register having eight data inputs, eight data outputs, a shift input, and a load input, wherein at least two of said eight data inputs are coupled to at least two of said eight input data signal lines, at least one of said eight data outputs is coupled to at least one of said four output data signal lines, said shift input is coupled to said shift signal line and said load input is coupled to said load signal line.
Claim 13
Dependent Claim
53 words
The circuit in claim 10 wherein a first of said eight data inputs receives a first bit of data from a first of said eight input data signal lines and a second of said eight data inputs receives a second bit of data from a second of said eight input data signal lines.
Claim 14
Dependent Claim
63 words
The circuit in claim 11 wherein said shift register transmits said first data bit from said first data input to a first of said eight data outputs and transmits said second data bit from said second data input to a second of said eight data outputs whenever said shift register receives a load signal from said load signal line on said load input.
Claim 15
Dependent Claim
41 words
The circuit in claim 12 wherein said shift register transmits said first data bit from said first data output to said second data output whenever said shift register receives a shift signal from said shift signal line on said shift input.
Claim 16
Dependent Claim
27 words
The circuit in claim 13 wherein said second data output is coupled to a first of said at least one of said four output data signal lines.
Claim 17
Dependent Claim
45 words
The circuit in claim 12 including a serial input signal line and wherein said shift register receives a serial input data bit from said serial input signal line on a serial input of said shift register which is coupled to said serial input signal line.
Claim 18
Dependent Claim
61 words
The circuit in claim 15 wherein said shift register transmits said first data bit from said first data output to said second data output and transmits said serial input data bit from said serial input of said shift register to said first data output whenever said shift register receives a shift signal from said shift signal line on said shift input.
Claim 19
Dependent Claim
27 words
The circuit in claim 16 wherein said first data output is coupled to a first of said at least one of said four output data signal lines.
Claim 20
Dependent Claim
35 words
The circuit in claim 16 wherein said shift register is called a "first shift register" and including a second shift register having a data output coupled to said serial input of said first shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-10 | 1998-10-10 | 1999-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-10 | 2002-10-10 | 2003-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-10 | 2006-10-10 | 2007-04-11 | $7700.00 | Window Closed / Lapsed |