Microcomputer having an error-correcting function based on a detected parity error

Claim 2

A microcomputer comprising: a data SRAM for storing data and outputting stored data; a parity SRAM, coupled to the data SRAM for storing a parity associated with each of the data stored in the data SRAM and for outputting the stored parity; a total-sum storage, coupled to the data SRAM, for storing a total sum of data associated with a block of stored data in the SRAM and for outputting the stored total sum of data; and a CPU for controlling the data SRAM, the parity SRAM and the total-sum storage, the CPU providing a summing function for calculating the total-sum of data associated with the block of stored data; a total-sum changing function for calculating a new total sum of data S new associated with the block of stored data when new data X new is stored in the block of stored data, the new total sum of data S new being based on an equation S.sub.new =S.sub.old +X.sub.new -X.sub.old, where, X new denotes new data after new data has been stored, the block of stored data replacing old data X old , and S old denotes an old total sum of data associated with the block of stored data before the new data is stored in the block of stored data; a parity adding function for calculating a vertical parity associated with the new data when the new data is stored in the data SRAM and for storing the vertical parity in the parity SRAM; a parity error detecting function for detecting an error in the vertical parity of data associated with the old data X old output from the parity SRAM when the old data X old is output from the data SRAM, and for producing an error indication when an error is detected in the output vertical parity; and an error correction function for calculating and correcting data stored at the address where the error has been detected by subtracting data stored at all addresses of the block of stored data other than the data stored at the address where the error has been detected from the new total sum of data S new associated with the block of stored data.

Claim 3

A microcomputer comprising: a data SRAM for storing data and outputting stored data; a parity SRAM, coupled to the data SRAM, for storing a parity associated with each of the data stored in the data SRAM and for outputting the stored parity; a total-sum storage, coupled to the data SRAM, for storing a total sum of data associated with a block of stored data in the SRAM and for outputting the stored total sum of data; a CPU for controlling the data SRAM, the parity SRAM and the total-sum storage; a total-sum changing unit, coupled to the SRAM, for changing the total sum of data associated with the block of stored data when data in the block of stored data and the associated parity in the parity SRAM are rewritten by the CPU, the total-sum changing unit calculating a new total sum of data S new associated with the block of stored data based on an equation S.sub.new =S.sub.old +X.sub.new -X.sub.old, where, X new denotes new data stored in the block of stored data, X old denotes old data stored in the block of stored data, and S old denotes an old total sum of data associated with the block of stored data before the new data X new is stored in the block of stored data; a parity adding unit, coupled to the SRAM and the parity SRAM, for calculating a vertical parity of data when data are stored in the data SRAM by the CPU, and for storing the calculated vertical parity in the parity SRAM; and a parity error detector, coupled to the parity SRAM, for detecting a vertical parity error of a vertical parity output from the parity SRAM when data are output from the data SRAM, and, when an error is detected in the output vertical parity, for outputting an address of the data where the error has been detected and for producing an error indication; the CPU having a summing function for calculating a total sum of data associated with the block of stored data and an error correcting function for calculating and correcting data at the address where the error has been detected by subtracting stored data at all addresses of the block of stored data other than the stored data at the address where the error has been detected from the new total sum of data S new associated with the block of stored data.

Claim 4

A microcomputer comprising: a data SRAM for storing data and outputting stored data; a parity SRAM, coupled to the data SRAM, for storing a parity associated with each of the data stored in the data SRAM and for outputting the stored parity; a total-sum storage, coupled to the data SRAM, for storing a total sum of data associated with a block of stored data in the SRAM and for outputting the stored total sum of data; a CPU for controlling the data SRAM, the parity SRAM and the total-sum storage; a total-sum changing unit, coupled to the SRAM, for changing the total sum of data associated with the block of stored data when data in the block of stored data and the associated parity in the parity SRAM are rewritten by the CPU, the total-sum changing unit calculating a new total sum of data S new associated with the block of stored data based on an equation S.sub.new =S.sub.old +X.sub.new -X.sub.old, where, X new denotes new data stored in the block of stored data, X old denotes old data stored in the block of stored data, and S old denotes an old total sum of data associated with the block of stored data before the new data X new is stored in the block of stored data; a parity adding unit, coupled to the SRAM and the parity SRAM, for calculating a vertical parity of data when data are stored in the data SRAM by the CPU, and for storing the calculated vertical parity in the parity SRAM; and a parity error detector, coupled to the parity SRAM, for detecting a vertical parity error of a vertical parity output from the parity SRAM when data are output from the data SRAM, and, when an error is detected in the output vertical parity, for outputting an address of the data where the error has been detected and for producing an error indication; the CPU having a summing function for calculating a total sum of data associated with the block of stored data and an error correcting function for calculating and correcting data at the address where the error has been detected by subtracting stored data at all addresses of the block of stored data other than the stored data at the address where the error has been detected from the new total sum of data S new associated with the block of stored data.