Multiprocessing system having a single translation lookaside buffer with reduced processor overhead

Claim 1

A multiprocessing system having a plurality of processors, one of which is a master processor and the other processors are slave processors, and a main memory connected to said plurality of processors, said main memory having a plurality of paged address translation tables stored respectively in logical memory spaces, each of said tables describing a relationship between a logical address and a physical address, said multiprocessing system comprising: means for receiving an instruction from a requesting processor, said instruction containing a segmented virtual space identifier (VSID) and a shared-access identifier or a nonshared-access identifier; a translation lookaside buffer (TLB) divided into TLB partitions; a plurality of registers respectively corresponding to said TLB partitions, each of said registers having first and second fields, said second field having bit positions respectively assigned to said plurality of processors; means, responsive to an instruction received by said receiving means containing a nonshared-access identifier, for selecting one of said registers, said second field of said selected register having all vacant bit positions, and writing said VSID into said first field of said selected register and setting a bit in a bit position of said selected register assigned to said requesting processor, making a search through said registers to detect a register having said VSID and first and second bits in positions respectively assigned to said master processor and said requesting processor, and resetting said second bit; means responsive to an instruction received by said receiving means containing a shared-access identifier, for making a search through said registers for detecting a first register having said VSID and a bit in a position assigned to said master processor, setting a bit in a position of said first register assigned to said requesting processor, and detecting a second register having said VSID and a bit in a position assigned to said requesting processor, and resetting said bit of said second register; table loading means, responsive to said nonshared-access identifier, for loading a copy of said paged address translation tables from said main memory into a TLB partition corresponding to a register having said VSID and a single bit in said second field thereof, said single bit being set in a position assigned to said requesting processor; and memory access means for accessing said main memory according to a physical address contained in a TLB partition corresponding to a register having said VSID and a bit in a position assigned to said requesting processor.