Apparatus and method for addressing a variable sized block of memory

Claim 2

An address aliasing device, which comprises: a size selector for generating memory size aliasing bits; an address input adapted to receive a multiple bit address for a memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for said preselected ones of the multiple bits as well as bits of the multiple bit address other than those preselected ones of the multiple bits.

Claim 5

An address aliasing device, which comprises: a memory size code storage device for storing a code indicative of a number of locations in a memory system that are available for use; a size selector coupled to the memory size code storage device to read and decode the code into corresponding memory size aliasing bits; an address input adapted to receive a multiple bit address for the memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 6

An address aliasing device, which comprises: a memory size code storage device for storing a code indicative of a number of locations in a memory system that are available for use; a size selector coupled to the memory size code storage device to read and decode the code into corresponding memory size aliasing bits; an address input adapted to receive a multiple bit address for the memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 7

The address aliasing device of claim 3 wherein the logic device comprises a set of OR gates; each of the OR gates including a first input for input of one of the memory size aliasing bits and a second input for input of a corresponding one of the preselected ones of the multiple bit memory address and each of the OR gates including an output lead; the output leads of the OR gates provide an output comprising the aliases for the preselected ones of the bits of the multiple bit address.

Claim 8

An address aliasing device, which comprises: a memory size code storage device storing a code indicative of a number of locations available for use in each of a plurality of memory storage spaces; a size selector coupled to the memory size code storage device; an address input adapted to receive a multiple bit address for one of the plurality of memory storage spaces; the size selector arranged to read and decode the code stored in the memory size code storage device to determine the number of locations available for use in one of the plurality of memory storage spaces as a function of the address received by the address input and to generate memory size aliasing bits as a function of the number of available locations in the one of the plurality of memory storage spaces; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the multiple bit address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 9

An address aliasing device, which comprises: a memory size code storage device storing a code indicative of a number of locations available for use in each of a plurality of memory storage spaces; a size selector coupled to the memory size code storage device; an address input adapted to receive a multiple bit address for one of the plurality of memory storage spaces; the size selector arranged to read and decode the code stored in the memory size code storage device to determine the number of locations available for use in one of the plurality of memory storage spaces as a function of the address received by the address input and to generate memory size aliasing bits as a function of the number of available locations in the one of the plurality of memory storage spaces; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the multiple bit address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 10

An address aliasing device, which comprises: a memory size code storage device which stores a code indicative of a number of locations in a memory system that are available for use in each of a plurality of memory storage spaces arranged in the memory system; a size selector coupled to the memory size code storage device to read and decode the code into corresponding memory size aliasing bits, wherein the size selector operates to determine the memory size aliasing bits of one of the plurality of memory storage spaces as a function of the code and the address received by an address input, said address input adapted to receive a multiple bit address for the memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits, wherein the logic device comprises a set of OR gates; each of the OR gates including a first input for input of one of the memory size aliasing bits and second input for input of a corresponding one of the preselected ones of the multiple bit memory address and each of the OR gates including an output; the outputs of the OR gates comprising the aliases for the preselected ones of the bits of the multiple bit address; and an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 11

An address aliasing device, which comprises: a memory size code storage device which stores a code indicative of a number of locations in a memory system that are available for use in each of a plurality of memory storage spaces arranged in the memory system; a size selector coupled to the memory size code storage device to read and decode the code into corresponding memory size aliasing bits, wherein the size selector operates to determine the memory size aliasing bits of one of the plurality of memory storage spaces as a function of the code and the address received by an address input, said address input adapted to receive a multiple bit address for the memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits, wherein the logic device comprises a set of OR gates; each of the OR gates including a first input for input of one of the memory size aliasing bits and second input for input of a corresponding one of the preselected ones of the multiple bit memory address and each of the OR gates including an output; the outputs of the OR gates comprising the aliases for the preselected ones of the bits of the multiple bit address; and an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 12

The address aliasing device of claim 6, wherein the memory size code storage device stores a multiple bit code divided into n bit sections, each n bit section being indicative of the number of locations available for use in a corresponding one of the plurality of memory storage spaces.

Claim 13

The address aliasing device of claim 7, wherein the size selector determines one of the n bit sections of the code as a function of the address received by the address input and the size selector further includes a size selector decoder to decode the n bit section of the code determined by the size selector into the memory size aliasing bits.

Claim 14

The address aliasing device of claim 8, wherein the size selector decoder comprises a look-up table having 2 n locations, each location storing memory size aliasing bits for a corresponding one of the n bit sections of the code and the one n bit section determined by the size selector being used as an index to the look-up table.

Claim 15

An address aliasing device, which comprises: a size selector for generating memory size aliasing bits including a storage device for storing a code indicative of a number of locations in the memory system that are available to a user and wherein the size selector decodes the code into the memory size aliasing bits; an address input adapted to receive a multiple bit address for a memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 16

An address aliasing device, which comprises: a size selector for generating memory size aliasing bits including a storage device for storing a code indicative of a number of locations in the memory system that are available to a user and wherein the size selector decodes the code into the memory size aliasing bits; an address input adapted to receive a multiple bit address for a memory system; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits.

Claim 17

The address aliasing device of claim 10, wherein the size selector comprises a look-up table for input of the code and output of corresponding memory size aliasing bits.

Claim 18

A computer system, which comprises: a plurality of processors; a memory device including read and write data ports and an address port; a bus for coupling the processors to one another and to the read and write data ports of the memory device; a size selector for generating memory size aliasing bits; an address input adapted to receive a multiple bit address from the memory device; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for said preselected ones of the multiple bits as well as bits of the multiple bit address other than those preselected ones of the multiple bits; the output lead being coupled to the address port of the memory device.

Claim 19

A computer system, which comprises: a plurality of processors; a memory device including read and write data ports and an address port; a bus for coupling the processors to one another and to the read and write data ports of the memory device; a size selector for generating memory size aliasing bits; an address input adapted to receive a multiple bit address from the memory device; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the address and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for said preselected ones of the multiple bits as well as bits of the multiple bit address other than those preselected ones of the multiple bits; the output lead being coupled to the address port of the memory device.

Claim 20

A computer system, which comprises: a plurality of processors; a memory system including a plurality of memory storage spaces, read and write data ports and an address port; a bus for coupling the processors to one another and to the read and write data ports of the memory system; a memory size code storage device for storing a code indicative of a number of locations available for use in each of a plurality of memory storage spaces of the memory system; an address input coupled to the bus and adapted to receive multiple bit addresses from the processors via the bus, each one of the multiple bit addresses identifying a location in one of the plurality of memory storage spaces; a size selector coupled to the memory size code storage device; the size selector arranged to read and decode the code stored in the memory size code storage device to determine the number of locations available for use in one of the plurality of memory storage spaces as a function of an address received by the address input from one of the processors via the bus and to generate memory size aliasing bits as a function of the number of available locations in the one of the plurality of memory storage spaces; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the multiple bit address received from the one of the processors and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits; the output lead being coupled to the address port of the memory system.

Claim 21

A computer system, which comprises: a plurality of processors; a memory system including a plurality of memory storage spaces, read and write data ports and an address port; a bus for coupling the processors to one another and to the read and write data ports of the memory system; a memory size code storage device for storing a code indicative of a number of locations available for use in each of a plurality of memory storage spaces of the memory system; an address input coupled to the bus and adapted to receive multiple bit addresses from the processors via the bus, each one of the multiple bit addresses identifying a location in one of the plurality of memory storage spaces; a size selector coupled to the memory size code storage device; the size selector arranged to read and decode the code stored in the memory size code storage device to determine the number of locations available for use in one of the plurality of memory storage spaces as a function of an address received by the address input from one of the processors via the bus and to generate memory size aliasing bits as a function of the number of available locations in the one of the plurality of memory storage spaces; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the multiple bit address received from the one of the processors and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits; the output lead being coupled to the address port of the memory system.

Claim 22

The computer system of claim 13, wherein the memory size code storage device is coupled to the bus for input of said code indicative of a number of locations available for use in each of said plurality of memory storage spaces of the memory system by one of said processors via the bus.

Claim 23

A computer system, which comprises: a plurality of processors; a memory device including read and write data ports and an address port; a bus for coupling the processors to one another and to the read and write data ports of the memory device; a memory size code storage device for storing a code indicative of a number of locations available for use in the memory device; an address input coupled to the bus and adapted to receive multiple bit addresses from the processors via the bus, each one of the multiple bit addresses identifying a location in the memory device; a size selector coupled to the memory size code storage device; the size selector arranged to read and decode the code into corresponding memory size aliasing bits; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the multiple bit address received from the one of the processors and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits; the output lead being coupled to the address port of the memory system.

Claim 24

A computer system, which comprises: a plurality of processors; a memory device including read and write data ports and an address port; a bus for coupling the processors to one another and to the read and write data ports of the memory device; a memory size code storage device for storing a code indicative of a number of locations available for use in the memory device; an address input coupled to the bus and adapted to receive multiple bit addresses from the processors via the bus, each one of the multiple bit addresses identifying a location in the memory device; a size selector coupled to the memory size code storage device; the size selector arranged to read and decode the code into corresponding memory size aliasing bits; a logic device coupled to each of the address input and the size selector for logically combining preselected ones of the multiple bits of the multiple bit address received from the one of the processors and the memory size aliasing bits to provide an alias for the preselected ones of the multiple bits; and an output lead for providing an output comprising the alias for the preselected ones of the multiple bits and bits of the multiple bit address other than the preselected ones of the multiple bits; the output lead being coupled to the address port of the memory system.

Claim 25

The computer system of claim 15, wherein the memory size code storage device is coupled to the bus for input of said code indicative of the number of locations available for use in the memory device by one of said processors via the bus.

Claim 26

The computer system of any one of claims 13, 15 or 12, wherein the logic device comprises a set of OR gates; each of the OR gates including a first input for input of one of the memory size aliasing bits and a second input for input of a corresponding one of the preselected ones of the multiple bits of the multiple bit address and each of the OR gates including an output; the outputs of the OR gates comprising the alias for preselected ones of the multiple bits of the multiple bit address.