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US5404405A Expired / Lapsed US ⏱️ 0.0 years remaining

FM stereo decoder and method using digital signal processing

Assignee: The AT&T MVPD Group LLC
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Filing: 1993-08-05
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Granted: 1995-04-04
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Expires: 2013-08-05
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Abstract

Abstract A digital FM stereo decoder uses the phase characteristics of linear phase FIR filters, together with a trignometric operation, to generate a 38 kHz subcarrier signal from a 19 kHz pilot. The subcarrier signal is mixed with the input composite signal from which the pilot has been removed to shift its L-R component to baseband; the linear phase FIR filters also maintain phase coherence between the subcarrier and the composite signals. A low distortion output is obtained without the use of a phase locked loop for the regeneration of the subcarrier signal.

Inventors

  • 👤 Kevin T. Collier
  • 👤 Kevin T. Chan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 01:03
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H04B1/1653

Claims Analysis

Total Claims: 30
Claim 1
Independent Claim 250 words
An FM stereo decoder using digital signal processing, comprising: a demodulator and analog-to-digital converter (ADC) for demodulating and converting an FM signal having an L+R (left+right) baseband signal, an L-R signal centered on a subcarrier frequency, and a pilot signal at less than the subcarrier frequency, to a digital demodulated composite signal, an analog-to-digital converter (ADC) for converting the FM signal to digital format, said demodulator and ADC together yielding a digital demodulated composite signal, a digital bandpass filter for extracting the pilot signal from said composite signal, a first digital delay filter for maintaining said composite signal in phase with the extracted pilot signal, a differencing node for removing the pilot signal from said composite signal by taking the difference between said composite signal and the in-phase extracted pilot signal, thereby yielding a pilot-free composite signal, a plurality of digital filters operating upon said extracted pilot signal to obtain a pair of filtered signals at the pilot signal frequency and in mutual phase quadrature relationship, a subcarrier frequency generator operating upon said mutual phase quadrature signals to obtain a mixing signal at the subcarrier frequency, a second digital delay filter for delaying said pilot-free composite signal to keep it in-phase with said mixing signal, a mixer for mixing said delayed pilot-free composite signal with said mixing signal to shift said L-R signal to a baseband frequency range, and an output processor for extracting said L and R signals from said delayed pilot-free composite signal and said baseband L-R signal.
Claim 2
Dependent Claim 250 words
An FM stereo decoder using digital signal processing, comprising: a demodulator and analog-to-digital converter (ADC) for demodulating and converting an FM signal having an L+R (left+right) baseband signal, an L-R signal centered on a subcarrier frequency, and a pilot signal at less than the subcarrier frequency, to a digital demodulated composite signal, an analog-to-digital converter (ADC) for converting the FM signal to digital format, said demodulator and ADC together yielding a digital demodulated composite signal, a digital bandpass filter for extracting the pilot signal from said composite signal, a first digital delay filter for maintaining said composite signal in phase with the extracted pilot signal, a differencing node for removing the pilot signal from said composite signal by taking the difference between said composite signal and the in-phase extracted pilot signal, thereby yielding a pilot-free composite signal, a plurality of digital filters operating upon said extracted pilot signal to obtain a pair of filtered signals at the pilot signal frequency and in mutual phase quadrature relationship, a subcarrier frequency generator operating upon said mutual phase quadrature signals to obtain a mixing signal at the subcarrier frequency, a second digital delay filter for delaying said pilot-free composite signal to keep it in-phase with said mixing signal, a mixer for mixing said delayed pilot-free composite signal with said mixing signal to shift said L-R signal to a baseband frequency range, and an output processor for extracting said L and R signals from said delayed pilot-free composite signal and said baseband L-R signal.
Claim 3
Dependent Claim 28 words
The FM stereo decoder of claim 1, said plurality of digital filters comprising a pair of filters having phase delay differences that differ from each other by 90°.
Claim 4
Dependent Claim 27 words
The FM stereo decoder of claim 2, said pair of filters comprising first and second linear phase finite impulse response (FIR) delay filters having a length N.
Claim 5
Dependent Claim 20 words
The FM stereo decoder of claim 3, wherein said digital filters have a length N, where (N-1)/2 is an integer.
Claim 6
Dependent Claim 23 words
The FM stereo decoder of claim 3, said first linear phase FIR delay filter performing a Hilbert transform upon said extracted pilot signal.
Claim 7
Dependent Claim 20 words
The FM stereo decoder of claim 5, wherein said digital filters have a length N, where (N-1)/2 is an integer.
Claim 8
Dependent Claim 27 words
The FM stereo decoder of claim 5, wherein said second digital delay filter comprises a linear phase FIR filter that also has a delay of (N-1)/2 samples.
Claim 9
Dependent Claim 39 words
The FM stereo decoder of claim 1, said digital bandpass filter comprising a plurality of linear phase FIR filters having respective sample lengths L, where ##EQU2## is an integer, and M is the number of linear phase FIR filters.
Claim 10
Dependent Claim 52 words
The FM stereo decoder of claim 1, said subcarrier frequency generator operating upon said pair of mutual phase quadrature signals at the pilot signal frequency to produce a signal at the subcarrier frequency in the form I 2 -Q 2 , where I and Q are the respective mutual phase quadrature signals.
Claim 11
Dependent Claim 32 words
The FM stereo decoder of claim 9, said subcarrier frequency generator dividing said I 2 -Q 2 signal by I 2 +Q 2 to obtain a normalized signal at the subcarrier frequency.
Claim 12
Dependent Claim 27 words
The FM stereo decoder of claim 10, said subcarrier frequency generator further multiplying said ##EQU3## signal by 2 prior to mixing with said delayed pilot-free composite signal.
Claim 13
Dependent Claim 14 words
The FM stereo decoder of claim 1, wherein said decoder is implemented in hardware.
Claim 14
Dependent Claim 20 words
The FM stereo decoder of claim 1, said decoder comprising a microprocessor programmed to implement said decoder functions in software.
Claim 15
Dependent Claim 112 words
A digital signal processor (DSP) for doubling the frequency of the pilot signal component of an input composite digital signal that has pilot and information signal components, the pilot signal having a given frequency ω, comprising: a digital bandpass filter arranged to extract said pilot signal component from said composite input signal, a plurality of digital filters operating upon said extracted pilot signal component to obtain a pair of filtered signals Q and I at the pilot signal frequency, where Q and I are in mutual phase quadrature at the frequency ω, and a frequency doubler operating upon said Q and I signals to obtain an input signal at the frequency 2ω.
Claim 16
Dependent Claim 112 words
A digital signal processor (DSP) for doubling the frequency of the pilot signal component of an input composite digital signal that has pilot and information signal components, the pilot signal having a given frequency ω, comprising: a digital bandpass filter arranged to extract said pilot signal component from said composite input signal, a plurality of digital filters operating upon said extracted pilot signal component to obtain a pair of filtered signals Q and I at the pilot signal frequency, where Q and I are in mutual phase quadrature at the frequency ω, and a frequency doubler operating upon said Q and I signals to obtain an input signal at the frequency 2ω.
Claim 17
Dependent Claim 93 words
A digital signal processor (DSP) for doubling the frequency of an input digital signal having a given frequency ω, comprising: a plurality of digital filters operating upon said input signal to obtain a pair of filtered signals Q and I, where Q and I are in mutual phase quadrature at the frequency ω, said plurality of digital filters comprising a pair of filters having phase delays that differ from each other by 90°, and a frequency doubler operating upon said Q and I signals to obtain an output signal at the frequency 2ω.
Claim 18
Dependent Claim 93 words
A digital signal processor (DSP) for doubling the frequency of an input digital signal having a given frequency ω, comprising: a plurality of digital filters operating upon said input signal to obtain a pair of filtered signals Q and I, where Q and I are in mutual phase quadrature at the frequency ω, said plurality of digital filters comprising a pair of filters having phase delays that differ from each other by 90°, and a frequency doubler operating upon said Q and I signals to obtain an output signal at the frequency 2ω.
Claim 19
Dependent Claim 25 words
The DSP of claim 15, said pair of filters comprising first and second linear phase finite impulse response (FIR) delay filters having a length N.
Claim 20
Dependent Claim 18 words
The DSP of claim 16, said first FIR delay filter performing a Hilbert transform upon said input signal.
Claim 21
Dependent Claim 21 words
The DSP of claim 17, wherein (N-1)/2 is an integer, and said second FIR delay filter comprises a (N-1)/2 sample delay.
Claim 22
Dependent Claim 32 words
The DSP of claim 14, said frequency doubler operating directly upon said Q and I signals to produce a signal with a frequency 2ω in the form I 2 -Q 2 .
Claim 23
Dependent Claim 27 words
The DSP of claim 19, said frequency doubler dividing said I 2 -Q 2 signal by I 2 +Q 2 to obtain a normalized 2ω frequency signal.
Claim 24
Dependent Claim 31 words
The DSP of claim 19, said plurality of digital filters comprising first and second linear phase finite impulse response (FIR) delay filters having a length N, where (N-1)/2 is an integer.
Claim 25
Dependent Claim 12 words
The DSP of claim 14, wherein said DSP is implemented in hardware.
Claim 26
Dependent Claim 19 words
The DSP of claim 14, comprising a microprocessor programmed to implement said digital filters and frequency doubler in software.
Claim 27
Independent Claim 120 words
A method of obtaining a mixing signal for mixing with a composite FM stereo signal, said composite signal having a pilot signal component at a frequency ω, an L+R (left+right) baseband signal, and an L-R signal centered on a subcarrier frequency 2ω comprising: extracting said pilot signal component from said composite signal, generating a pair of signals Q and I from said extracted pilot signal component at the pilot signal frequency ω in mutual phase quadrature, squaring said Q and I signals to obtain signals in the form Q 2 and I 2 , and subtracting the Q 2 signal from the I 2 signal to obtain a signal in the form I 2 -Q 2 at the frequency 2ω.
Claim 28
Independent Claim 120 words
A method of obtaining a mixing signal for mixing with a composite FM stereo signal, said composite signal having a pilot signal component at a frequency ω, an L+R (left+right) baseband signal, and an L-R signal centered on a subcarrier frequency 2ω comprising: extracting said pilot signal component from said composite signal, generating a pair of signals Q and I from said extracted pilot signal component at the pilot signal frequency ω in mutual phase quadrature, squaring said Q and I signals to obtain signals in the form Q 2 and I 2 , and subtracting the Q 2 signal from the I 2 signal to obtain a signal in the form I 2 -Q 2 at the frequency 2ω.
Claim 29
Dependent Claim 48 words
The method of claim 24, wherein said Q and I signals are digital signals and are generated by processing said extracted pilot signal component at the frequency ω through a pair of linear phase finite impulse response (FIR) delay filters having lengths N, where (N-1)/2 is an integer.
Claim 30
Dependent Claim 48 words
The method of claim 24, further comprising the step of adding said I 2 and Q 2 signals to obtain a signal in the form I 2 +Q 2 , and normalizing said I 2 -Q 2 signal by dividing it by said I 2 +Q 2 signal.

References Cited (Backward Citations)

US4652838A Cited
US5249203A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-03 1998-10-03 1999-04-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-04-03 2002-10-03 2003-04-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-04-03 2006-10-03 2007-04-04 $7700.00 Window Closed / Lapsed

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