Method and apparatus for converting scanning line of a video signal receiver

Claim 3

The method according to claim 1 wherein the step of combining comprises, for each delayed line j and successive undelayed line j+1; multiplying said delayed line j by a constant K 1 ; multiplying said undelayed line j+1 by a constant K 2 ; and summing the products of said multiplications to form a single NTSC line, wherein the sum of the constants K 1 and K 2 is substantially equal to 1, and wherein the values of constants K 1 and K 2 vary depending on the line numbers within said N+1 unit that are being combined.

Claim 4

The method according to claim 2 wherein N is equal to 5, and wherein each unit of six PAL lines, 1p, 2p . . . 6p, is converted into five NTSC lines 1n, 2n, . . . 5n, containing the data from said six PAL lines.

Claim 5

The method of claim 3, wherein said six PAL lines are combined as follows to form said five NTSC lines: (1p)(K.sub.1,1)+(2p)(K.sub.2,1)=1n (2p)(K.sub.1,2)+(3p)(K.sub.2,2)=2n (3p)(K.sub.1,3)+(4p)(K.sub.2,3)=3n (4p)(K.sub.1,4)+(5p)(K.sub.2,4)=4n (5p)(K.sub.1,5)+(6p)(K.sub.2,5)=5n wherein K 1 ,n +K 2 ,n =1, for all values of n from 1 through 5.

Claim 6

The method of claim 4 wherein the values of K are: (K.sub.1,1)=(K.sub.2,5)=0.833 (K.sub.2,1)=(K.sub.2,5)=0.166 (K.sub.1,2)=(K.sub.2,4)=0.66 (K.sub.2,2)=(K.sub.1,4)=0.33 (K.sub.1,3)=(K.sub.2,3)=0.5.

Claim 9

The method of claim 6 wherein the step of combining said two successive lines of NTSC lines, comprises, for each delayed line j and undelayed line j+1; multiplying said delayed line j by a constant K 1 ,j, and said undelayed line by a constant K 2 ,j, summing the products of said multiplications to form a single PAL line, wherein the sum of the constants K 1 ,j +K 2 ,j is substantially equal to 1 and wherein the values of constants K 1 ,j and K 2 ,j vary depending on the line numbers within said conversion units.

Claim 10

The method according to claim 7 wherein N is equal to 5 and wherein each unit of five NTSC lines, 1n, 2n3n4n, 5n is converted into six lines of PAL, 1p, 2p , . . . 6p.

Claim 11

The method of claim 8 wherein said five NTSC lines are combined as follows to form six PAL lines: (-)(K.sub.1,1)+(1n)(K.sub.2,1)=1p (1n)(K.sub.1,2)+(2n)(K.sub.2,2)=2p (2n)(K.sub.1,3)+(3n)(K.sub.2,3)=3p (3n)(K.sub.1,4)+(4n)(K.sub.2,4)=4p (4n)(K.sub.1,5)+(5n)(K.sub.2,5)=5p (5n)(K.sub.1,6)+(-)(K.sub.2,6)=6p.

Claim 12

The method of claim 9 wherein said constants K 1 ,j and K 2 ,j are as follows: (K.sub.1,1)=(K.sub.2,6)=0 (K.sub.2,1)=(K.sub.1,6)=1 (K.sub.1,2)=(K.sub.2,5)=0.2 (K.sub.2,2)=(K.sub.1,5)=0.8 (K.sub.1,3)=(K.sub.2,4)=0.4 (K.sub.2,3)=(K.sub.1,4)=0.6

Claim 13

A scanning line converting apparatus for video signals, comprising: an A/D converting circuit for converting Y and C signals to digital signals; line memory means for storing 1H lines, and for providing 1H delayed data; a percent block for providing a ratio for every 1H line; an arithmetic circuit for providing line-converted outputs after computing outputs in response to respective line constants based on said ratios provided by said percent block, the digital signals of said Y and C signals of said A/D converting circuit, and said 1H delayed output of said line memory means; and a picture memory for receiving the output of said arithmetic circuit, and for storing and providing picture data under the control of memory control holding signals of said percent block.

Claim 14

A scanning line converting apparatus for video signals, comprising: an A/D converting circuit for converting Y and C signals to digital signals; line memory means for storing 1H lines, and for providing 1H delayed data; a percent block for providing a ratio for every 1H line; an arithmetic circuit for providing line-converted outputs after computing outputs in response to respective line constants based on said ratios provided by said percent block, the digital signals of said Y and C signals of said A/D converting circuit, and said 1H delayed output of said line memory means; and a picture memory for receiving the output of said arithmetic circuit, and for storing and providing picture data under the control of memory control holding signals of said percent block.

Claim 15

The scanning line converting apparatus for video signals as claimed in claim 11, wherein said percent block comprises: a 6-bit counter 310 for repeatedly counting horizontal synchronizing signals to count 6 outputs using 6 horizontal synchronizing signals as the periods, and for being cleared by vertical blanking signals; and a logic combining circuit 320 for receiving low signals under input signals of 625 lines, for receiving high signals under input signals of 525 lines, for providing constants for respective horizontal scanning lines through 8 percent output terminals PER0, PER1, . . . , PER7 after logic-combining the outputs of said counter 310, and for generating control holding signals to said line memory means 200.

Claim 16

The scanning line converting apparatus for video signals as claimed in claim 12, wherein said arithmetic circuit 400 comprises: an arithmetic unit 410 for receiving Y signals of 1H delayed scanning lines of said line memory means 200, and for computing said Y signals in relation with inverted signals of said percent block 300 before providing it; an arithmetic unit 420 for receiving 1H delayed the digital converted Y signals for the current line from said A/D converting circuit 100, and for computing said Y signal data in relation with signals furnished by said percent block 300; an arithmetic unit 430 for performing computation by using C signals of 1H delayed scanning lines and an inverting signals of percent block output signals; an arithmetic unit 440 for receiving digital converted C signals for the current lines from said A/D converting circuit 100, and for computing signals of said percent block 300 in relation with said C signal data; an adding section 450 for providing Y signals of converted scanning lines after summing up the outputs of said arithmetic units 410 and 420; and an adding section 460 for providing C signals of converted scanning lines after summing up the outputs of said arithmetic units 430 and 440.

Claim 17

The line converting apparatus for video signals as claimed in claim 13, wherein each of said arithmetic units 410-440 comprises: a buffer BF1 for receiving 8-bit scanning line data from said A/D converting circuit 100 or from said line memory; multiplexers MUX1-MUX8 for receiving said 8-bit data from said buffer BF1, and for generating outputs after receipt of 8 logic signals simultaneously output from said percent block 300; adders ADD1-ADD4 of 9 bits, 7 bits, 5 bits and 3 bits for receiving two outputs from among said multiplexers MUX1 and MUX2, and for receiving data into their lower bits after sequentially decreasing the upper bits of the outputs of said multiplexers MMUX1-MUX8; adders ADD10 and ADD20 of 10 bits for receiving the 9-bit, 7-bit, 5-bit and 3-bit outputs of said adders ADD1-ADD4 of 9 bits, 7 bits, 5 bits and 3 bits after being increment the number of digits; an adder ADD30 for receiving both of the outputs of said adders ADD10 and ADD20, and for providing an 8-bit output; and a buffer BF2 for receiving the output of said adder ADD30, and for providing computed output signals.