US5404070A
Expired / Lapsed
US
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Low capacitance field emission display by gate-cathode dielectric
Assignee: Transpacific IP Ltd
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Filing: 1993-10-04
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Granted: 1995-04-04
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Expires: 2013-10-04
Abstract
Abstract A method for making a matrix addressed flat panel display using field emission microtips having reduced capacitance and low power consumption, and the resulting display, are described. A dielectric base substrate on which to form the field emission microtips is provided. Cathode columns of parallel spaced conductors are formed upon the substrate. First dielectric supports are formed in and above spaces between the cathode columns. Gate lines for the display are formed of parallel spaced conductors over the supports and perpendicular to the supports and the cathode columns. Second dielectric supports are formed below spaces between the gate lines, on the cathode columns and intersecting with the first supports. Pixels of the display are formed at the intersections of the cathode columns and the gate lines. There are a plurality of openings in the gate lines, at the pixels. A plurality of field emission microtips are formed at each of the pixels, connected to and extending up from the cathode columns and into the plurality of openings.
Inventors
- 👤 Chun-hui Tsai
- 👤 Jammy C. Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:37
CPC Classifications
H; H01; H01J; H01J9/00; H01J9/02; H01J9/022; H01J9/025; H01J2329/00
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
139 words
A matrix addressed flat panel display with field emission microtips and reduced capacitance, comprising: a dielectric base substrate; cathode columns for said display, formed of parallel spaced conductors upon said substrate; first dielectric supports in and above spaces between said cathode columns; gate lines for said display, formed of parallel spaced conductors, above and perpendicular to said first dielectric supports and said cathode columns; second dielectric supports below spaces between said gate lines, formed on said cathode columns and intersecting with said first supports; pixels of said display at the intersections of said cathode columns and said gate lines; a plurality of openings in said gate lines, at each of said pixels; and a plurality of field emission microtips at each of said pixels, connected to and extending up from said cathode columns and into said plurality of openings.
Claim 2
Dependent Claim
139 words
A matrix addressed flat panel display with field emission microtips and reduced capacitance, comprising: a dielectric base substrate; cathode columns for said display, formed of parallel spaced conductors upon said substrate; first dielectric supports in and above spaces between said cathode columns; gate lines for said display, formed of parallel spaced conductors, above and perpendicular to said first dielectric supports and said cathode columns; second dielectric supports below spaces between said gate lines, formed on said cathode columns and intersecting with said first supports; pixels of said display at the intersections of said cathode columns and said gate lines; a plurality of openings in said gate lines, at each of said pixels; and a plurality of field emission microtips at each of said pixels, connected to and extending up from said cathode columns and into said plurality of openings.
Claim 3
Dependent Claim
30 words
The flat panel display of claim 1 further comprising enhancement supports between said gate lines and said cathode columns, within said pixels, parallel to said first and second dielectric supports.
Claim 4
Dependent Claim
24 words
The flat panel display of claim 2 wherein there are between about 2 and 10,000 of said field emission microtips between said enhancement supports.
Claim 5
Dependent Claim
12 words
The flat panel display of claim 1 wherein said microtips are conical.
Claim 6
Dependent Claim
12 words
The flat panel display of claim 1 wherein said microtips are wedge-shaped.
Claim 7
Dependent Claim
20 words
The flat panel display of claim 1 wherein said first and second dielectric supports are formed of a silicon oxide.
Claim 8
Dependent Claim
19 words
The flat panel display of claim 1 wherein said first and second dielectric supports are formed of silicon nitride.
Claim 9
Independent Claim
161 words
A method of fabricating a matrix addressed flat panel display having cathode columns, gate lines and field emission microtips and reduced capacitance, comprising the steps of: providing a dielectric base substrate; forming parallel spaced conductors, acting as said cathode columns for said display, upon said substrate; forming a dielectric layer over said cathode columns and said substrate; forming parallel spaced conductors, acting as gate lines for said display, over said dielectric layer, and perpendicular to said cathode columns, the intersections of said cathode columns and gate lines being pixels of said display; forming a plurality of openings in said gate lines, at each of said pixels; forming dielectric supports, by etching said dielectric layer at said pixels, in and above spaces between said cathode columns, and below spaces between said gate lines; and forming at each of said pixels a plurality of field emission microtips connected to and extending up from said cathode conductor columns and into said plurality of openings.
Claim 10
Independent Claim
161 words
A method of fabricating a matrix addressed flat panel display having cathode columns, gate lines and field emission microtips and reduced capacitance, comprising the steps of: providing a dielectric base substrate; forming parallel spaced conductors, acting as said cathode columns for said display, upon said substrate; forming a dielectric layer over said cathode columns and said substrate; forming parallel spaced conductors, acting as gate lines for said display, over said dielectric layer, and perpendicular to said cathode columns, the intersections of said cathode columns and gate lines being pixels of said display; forming a plurality of openings in said gate lines, at each of said pixels; forming dielectric supports, by etching said dielectric layer at said pixels, in and above spaces between said cathode columns, and below spaces between said gate lines; and forming at each of said pixels a plurality of field emission microtips connected to and extending up from said cathode conductor columns and into said plurality of openings.
Claim 11
Dependent Claim
62 words
The method of claim 8 wherein the step of forming a plurality of field emission microtips comprises the steps of: forming a sacrificial layer on said gate layer; forming said field emission microtips by vertical evaporation of a conductive material; and removing said sacrificial layer, and excess conductive material formed on said sacrificial layer during said forming of said field emission microtips.
Claim 12
Dependent Claim
25 words
The method of claim 9 wherein the steps of removing said sacrificial layer and etching said dielectric layer to form dielectric supporters, are accomplished simultaneously.
Claim 13
Dependent Claim
25 words
The step of claim 8 of forming dielectric supports further comprising forming enhancement supports in areas within said pixel region other than under said openings.
Claim 14
Dependent Claim
28 words
The method of claim 8 wherein said dielectric layer is a silicon oxide and said etching of said dielectric supports is a wet etch with buffered hydrofluoric acid.
Claim 15
Dependent Claim
26 words
The method of claim 8 wherein said dielectric layer is silicon nitride and said etching of said dielectric supports is a wet etch with phosphoric acid.
Claim 16
Dependent Claim
19 words
The method of claim 8 wherein the thickness of said dielectric layer is between about 10,000 and 15,000 Angstroms.
Claim 17
Dependent Claim
137 words
A matrix addressed flat panel display with field emission microtips and reduced capacitance, comprising: a dielectric base substrate; cathode columns for said display, formed of parallel, slotted, spaced conductors upon said substrate; gate lines for said display, formed of parallel, slotted, spaced conductors, over and perpendicular to said cathode columns; pixels of said display at the intersections of said cathode columns and said gate lines; a plurality of openings in said gate lines, at each of said pixels; a plurality of field emission microtips at each of said pixels, connected to and extending up from said cathode columns and into said plurality of openings; and dielectric supports, formed on said substrate in slots of said cathode columns, between said field emitter microtips, and rising up to connect to said gate line between slots of said gate line.
Claim 18
Dependent Claim
137 words
A matrix addressed flat panel display with field emission microtips and reduced capacitance, comprising: a dielectric base substrate; cathode columns for said display, formed of parallel, slotted, spaced conductors upon said substrate; gate lines for said display, formed of parallel, slotted, spaced conductors, over and perpendicular to said cathode columns; pixels of said display at the intersections of said cathode columns and said gate lines; a plurality of openings in said gate lines, at each of said pixels; a plurality of field emission microtips at each of said pixels, connected to and extending up from said cathode columns and into said plurality of openings; and dielectric supports, formed on said substrate in slots of said cathode columns, between said field emitter microtips, and rising up to connect to said gate line between slots of said gate line.
Claim 19
Dependent Claim
25 words
The flat panel display of claim 15 wherein there are between about 2 and 10,000 of said field emission microtips at each of said pixels.
Claim 20
Dependent Claim
17 words
The flat panel display of claim 15 wherein said dielectric supports are formed of a silicon oxide.
Claim 21
Dependent Claim
16 words
The flat panel display of claim 15 wherein said dielectric supports are formed of silicon nitride.
Claim 22
Independent Claim
174 words
A method of fabricating a matrix addressed flat panel display having cathode columns, gate lines and field emission microtips and reduced capacitance, comprising the steps of: providing a dielectric base substrate; forming parallel, spaced, slotted conductors, acting as said cathode columns for said display, upon said substrate; forming a dielectric layer over said cathode columns and said substrate; forming parallel, spaced, slotted conductors, acting as gate lines for said display, over said dielectric layer, and perpendicular to said cathode columns, the intersections of said cathode columns and gate lines being pixels of said display; forming a plurality of openings in said gate lines, at each of said pixels; etching said dielectric layer at said pixels, to form dielectric supports in slots of said cathode columns, between said field emitter microtips, and rising up to connect to said gate line between slots of said gate line; and forming at each of said pixels a plurality of field emission microtips connected to and extending up from said cathode conductor columns and into said plurality of openings.
Claim 23
Independent Claim
174 words
A method of fabricating a matrix addressed flat panel display having cathode columns, gate lines and field emission microtips and reduced capacitance, comprising the steps of: providing a dielectric base substrate; forming parallel, spaced, slotted conductors, acting as said cathode columns for said display, upon said substrate; forming a dielectric layer over said cathode columns and said substrate; forming parallel, spaced, slotted conductors, acting as gate lines for said display, over said dielectric layer, and perpendicular to said cathode columns, the intersections of said cathode columns and gate lines being pixels of said display; forming a plurality of openings in said gate lines, at each of said pixels; etching said dielectric layer at said pixels, to form dielectric supports in slots of said cathode columns, between said field emitter microtips, and rising up to connect to said gate line between slots of said gate line; and forming at each of said pixels a plurality of field emission microtips connected to and extending up from said cathode conductor columns and into said plurality of openings.
Claim 24
Dependent Claim
62 words
The method of claim 19 wherein the step of forming a plurality of field emission microtips comprises the steps of: forming a sacrificial layer on said gate layer; forming said field emission microtips by vertical evaporation of a conductive material; and removing said sacrificial layer, and excess conductive material formed on said sacrificial layer during said forming of said field emission microtips.
Claim 25
Dependent Claim
28 words
The method of claim 19 wherein said dielectric layer is a silicon oxide and said etching of said dielectric supports is a wet etch with buffered hydrofluoric acid.
Claim 26
Dependent Claim
26 words
The method of claim 19 wherein said dielectric layer is silicon nitride and said etching of said dielectric supports is a wet etch with phosphoric acid.
Claim 27
Dependent Claim
19 words
The method of claim 19 wherein the thickness of said dielectric layer is between about 10,000 and 15,000 Angstroms.
Claim 28
Dependent Claim
26 words
The method of claim 19 wherein said slots in said cathode columns are formed contiguously between said emitters running parallel to direction of said cathode columns.
Claim 29
Dependent Claim
26 words
The method of claim 19 wherein said slots in said gate lines are formed contiguously between said openings running parallel to direction of said gate lines.
References Cited (Backward Citations)
US3755704A
Cited
US4763187A
Cited
US4763187B1
Cited
US4908539A
Cited
US4857161A
Cited
US4884010A
Cited
US4874981A
Cited
US5075591A
Cited
US5141459A
Cited
US5103145A
Cited
US5103144A
Cited
US5151061A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |