US5403420A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication tool and method for parallel processor structure and package
Assignee: International Business Machines Corp
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Filing: 1993-07-27
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Granted: 1995-04-04
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Expires: 2013-07-27
Abstract
Abstract Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.
Inventors
- 👤 Thomas P. Gall
- 👤 James R. Loomis
- 👤 David B. Stone
- 👤 Cheryl L. Tytran
- 👤 James Wilcox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:06
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4611; H05K3/4614; H05K3/462; B; B32; B32B; B32B37/00; B32B37/12; B32B37/1207; B32B2327/00; B32B2327/12; B32B2379/00; B32B2457/00; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/015; H05K2201/0154; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09536; H05K2203/00; H05K2203/06; H05K2203/068; H05K3/4623; H05K3/4641; H05K3/4688; H05K3/4691; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49105
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
392 words
A method of fabricating a parallel processor laminate structure having a plurality of processor integrated circuit chips, and a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon; b. said printed circuit cards and boards are mounted on a plurality of perfluorocarbon polymer circuitized flexible layers, said circuitized perfluorocarbon polymer flexible layers having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and c. said circuitized perfluorocarbon polymer flexible layers are joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible layers at their signal interconnection circuitization portions, whereby said circuitized flexible layers are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions; said process comprising placing a stack of perfluorocarbon polymer flexible layers to be joined into a lamination fixture, said lamination fixture being between a pair of platens, and separated from said pair of platens by at least one coefficient of thermal expansion matching plate, and by a pair of release layers, said fixture being substantially conformal to the shape of the stack of flexible layers, and being separated from the top and bottom of the stack of flexible layers by release layers, said method further comprising applying a pressure above about 300 psi and a temperature above about 390 degrees Celsius to the stack of flexible layers while selectively defining and controlling the adhesion between the flexible layers within and beyond the laminate structure.
Claim 2
Independent Claim
392 words
A method of fabricating a parallel processor laminate structure having a plurality of processor integrated circuit chips, and a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon; b. said printed circuit cards and boards are mounted on a plurality of perfluorocarbon polymer circuitized flexible layers, said circuitized perfluorocarbon polymer flexible layers having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and c. said circuitized perfluorocarbon polymer flexible layers are joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible layers at their signal interconnection circuitization portions, whereby said circuitized flexible layers are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions; said process comprising placing a stack of perfluorocarbon polymer flexible layers to be joined into a lamination fixture, said lamination fixture being between a pair of platens, and separated from said pair of platens by at least one coefficient of thermal expansion matching plate, and by a pair of release layers, said fixture being substantially conformal to the shape of the stack of flexible layers, and being separated from the top and bottom of the stack of flexible layers by release layers, said method further comprising applying a pressure above about 300 psi and a temperature above about 390 degrees Celsius to the stack of flexible layers while selectively defining and controlling the adhesion between the flexible layers within and beyond the laminate structure.
Claim 3
Dependent Claim
39 words
The method of claim 1 comprising providing a low melting adhesive compatible with the perfluorocarbon polymer between the layers in the regions intended to be laminated, and thereafter heating the stack of flexible layers to effect adhesion and lamination.
Claim 4
Dependent Claim
19 words
The method of claim 2 wherein the low melting adhesive compatible with the perfluorocarbon polymer is a thermoplastic polyimide.
Claim 5
Dependent Claim
31 words
The method of claim 3 wherein the thermoplastic polyimide is chosen from the group consisting of benzophenone tetracarboxylic acid dianhydride-oxydianiline-metaphenylenediamine (BTDA-ODA-MPD), biphenyl-3,3',4,4' tetracarboxylic acid dianhydride-4,4'-hexafluoropropylidene diamine (BPDA-6FDAM), and 4,4'-hexafluoroisopropylidene dianhydride-oxydianiline (6FDA-ODA).
Claim 6
Dependent Claim
67 words
The method of claim 1 comprising providing a high melting mask compatible with the perfluorocarbon polymer between the perfluorocarbon polymer circuitized flex layers in the regions not intended to be laminated, and thereafter stacking the circuitized perfluorocarbon polymer flex layers and heating the stack to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
Claim 7
Dependent Claim
19 words
The method of claim 5 wherein the high melting mask is biphenyl tetracarboxylic acid dianhydride-phenylene diamine (BPDA-PDA) polyamic acid.
Claim 8
Dependent Claim
42 words
The method of claim 6 comprising drawing down the biphenyl tetracarboxylic acid dianhydride-phenylene diamine (BPDA-PDA) polyamic acid onto surfaces of the polyimide dielectric not intended to be laminated, and thereafter curing the biphenyl tetracarboxylic acid dianhydride-phenylene diamine (BPDA-PDA) to the corresponding polyimide.
Claim 9
Dependent Claim
33 words
The method of claim 6 comprising applying the biphenyl tetracarboxylic acid dianhydride-phenylene diamine (BPDA-PDA) as a free standing film, and laminating the polyimide dielectric above its melting temperature but below its imidization temperature.
Claim 10
Dependent Claim
109 words
The method of claim 1 comprising a. providing a low melting adhesive compatible with the perfluorocarbon polymer between the circuitized perfluorocarbon polymer flexible layers in the regions intended to be laminated, and thereafter stacking a first subassembly above a second subassembly and heating the subassembly stack to effect adhesion and lamination; and b. providing a high melting mask compatible with the perfluorocarbon polymer between the perfluorocarbon polymer circuitized flexible layers in the regions not intended to be laminated, and thereafter heating the stack circuitized flex strips to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
References Cited (Backward Citations)
US2444026A
Cited
JPS6183998A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |