Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit operative in a plurality of different modes, the semiconductor integrated circuit comprising: a plurality of input terminals; a plurality of resistive devices each connected between a corresponding one of the input terminals and a reference terminal to which a reference potential of the semiconductor integrated circuit is applied; a plurality of logic circuits each connected to a corresponding one of the input terminals and the resistive devices, each logic circuit generating a mode selection signal corresponding to one of the different modes when a predetermined potential is applied to one of the logic circuits from a corresponding one of the input terminals, the semiconductor integrated circuit thereby operating in a mode corresponding to the mode selection signal, and wherein a resistance of each resistive device is high enough such that an application of the predetermined potential to the one of the input terminals causes a voltage level of the one of the input terminals to be higher than a threshold voltage of the one of the logic circuits; detecting means, connected to the plurality of logic circuits, for generating a mode stop signal when at least two mode selection signals are simultaneously generated; and operation stopping means, operating in response to the mode stop signal, for stopping the operation of the semiconductor integrated circuit.

Claim 3

The semiconductor integrated circuit of claim 1, wherein said detecting means comprises: a plurality of means for NANDing at least two select signals of a plurality of select signals; and means for NANDing output signals of a plurality of said NANDing means and for outputting a detect signal when at least two operation modes are selected simultaneously.

Claim 4

The semiconductor integrated circuit of claim 1, wherein said operation stopping means comprises gating means for applying signals required for predetermined operation of the semiconductor integrated circuit to a predetermined circuit in the semiconductor integrated circuit, said gating means stopping the gate function thereof in response to a detect signal.

Claim 5

The semiconductor integrated circuit of claim 1, wherein each input terminal comprises a bonding pad that is connectable to a power supply terminal with wiring.

Claim 6

The semiconductor integrated circuit of claim 1, wherein each resistive device comprises an N channel transistor having a drain connected to a corresponding one of the input terminals, a gate connected to a power supply terminal to which a power supply voltage is applied, and a source connected to the reference terminal to which the reference potential of a ground level is applied.

Claim 7

The semiconductor integrated circuit of claim 1, wherein each resistive device comprises a P channel transistor having a source connected to a corresponding one of the input terminals, a drain connected to the reference terminal to which the reference potential of a power supply level is applied, and a gate connected to a ground terminal.

Claim 8

The semiconductor integrated circuit of claim 1, wherein each logic circuit comprises an inverter connected between a corresponding one of the resistive devices and the detecting means.

Claim 9

A semiconductor integrated circuit operative in a plurality of different modes, the semiconductor integrated circuit comprising: a plurality of input terminals; a plurality of resistive devices each connected between a corresponding one of the input terminals and a reference terminal to which a reference potential of the semiconductor integrated circuit is applied; a plurality of logic circuits each connected to a corresponding one of the input terminals and the resistive devices, each logic circuit generating a mode selection signal corresponding to one of the different modes when a predetermined potential is applied to one of the logic circuits from a corresponding one of the input terminals, and wherein a resistance of each resistive device is high enough such that an application of the predetermined potential to the one of the input terminals causes a voltage level of the one of the input terminals to be higher than a threshold voltage of the one of the logic circuits; and mode selection means for selecting one mode selection signal when at least two mode selection signals are generated, the semiconductor integrated circuit thereby operating in a mode corresponding to the selected mode selection signal.

Claim 10

A semiconductor integrated circuit operative in a plurality of different modes, the semiconductor integrated circuit comprising: a plurality of input terminals; a plurality of resistive devices each connected between a corresponding one of the input terminals and a reference terminal to which a reference potential of the semiconductor integrated circuit is applied; a plurality of logic circuits each connected to a corresponding one of the input terminals and the resistive devices, each logic circuit generating a mode selection signal corresponding to one of the different modes when a predetermined potential is applied to one of the logic circuits from a corresponding one of the input terminals, and wherein a resistance of each resistive device is high enough such that an application of the predetermined potential to the one of the input terminals causes a voltage level of the one of the input terminals to be higher than a threshold voltage of the one of the logic circuits; and mode selection means for selecting one mode selection signal when at least two mode selection signals are generated, the semiconductor integrated circuit thereby operating in a mode corresponding to the selected mode selection signal.

Claim 11

The semiconductor integrated circuit of claim 8, wherein each input terminal comprises a bonding pad that is connectable to a power supply terminal with wiring.

Claim 12

The semiconductor integrated circuit of claim 8, wherein each resistive device comprises an N channel transistor having a drain connected to a corresponding one of the input terminals, a gate connected to a power supply terminal to which a power supply voltage is applied, and a source connected to the reference terminal to which the reference potential of a ground level is applied.

Claim 13

The semiconductor integrated circuit of claim 8, wherein each resistive device comprises a P channel transistor having a source connected to a corresponding one of the input terminals, a drain connected to the reference terminal to which the reference potential of a power supply level is applied, and a gate connected to a ground terminal.

Claim 14

The semiconductor integrated circuit of claim 8, wherein each logic circuit comprises an inverter connected to a corresponding one of the resistive devices.

Claim 15

The semiconductor integrated circuit of claim 8, further comprising: current generating means, operative in response to the mode selection signal, for generating a current corresponding to the mode selection signal; and at least one observation terminal connected to an output of the current generating means, a mode selection signal thereby being observable as a current at an observation terminal.

Claim 16

A semiconductor integrated circuit operative in a plurality of different modes, the semiconductor integrated circuit comprising: a plurality of input terminals; a plurality of resistive devices each connected between a corresponding one of the input terminals and a reference terminal to which a reference potential of the semiconductor integrated circuit is applied; a plurality of logic circuits, an input of each logic circuit connected to a corresponding one of the input terminals and to a corresponding one of the resistive devices, each logic circuit generating a mode selection signal corresponding to one of the different modes when a predetermined potential is applied from a corresponding one of the input terminals, the semiconductor integrated circuit thereby operating in a mode corresponding to the mode selection signal, and wherein a resistance of each resistive device is high enough such that an application of the predetermined potential to one of the input terminals of one of the logic circuits causes a voltage level of the one of the input terminals to be higher than a threshold voltage of the one of the logic circuits; current generating means, operative in response to the mode selection signal, for generating a current corresponding to the mode selection signal; and at least one observation terminal connected to the current generating means, the mode selection signal thereby being observable as a current at the observation terminal.

Claim 17

A semiconductor integrated circuit operative in a plurality of different modes, the semiconductor integrated circuit comprising: a plurality of input terminals; a plurality of resistive devices each connected between a corresponding one of the input terminals and a reference terminal to which a reference potential of the semiconductor integrated circuit is applied; a plurality of logic circuits, an input of each logic circuit connected to a corresponding one of the input terminals and to a corresponding one of the resistive devices, each logic circuit generating a mode selection signal corresponding to one of the different modes when a predetermined potential is applied from a corresponding one of the input terminals, the semiconductor integrated circuit thereby operating in a mode corresponding to the mode selection signal, and wherein a resistance of each resistive device is high enough such that an application of the predetermined potential to one of the input terminals of one of the logic circuits causes a voltage level of the one of the input terminals to be higher than a threshold voltage of the one of the logic circuits; current generating means, operative in response to the mode selection signal, for generating a current corresponding to the mode selection signal; and at least one observation terminal connected to the current generating means, the mode selection signal thereby being observable as a current at the observation terminal.

Claim 18

The semiconductor integrated circuit of claim 14, wherein each input terminal comprises a bonding pad that is connectable to a power supply terminal with wiring.

Claim 19

The semiconductor integrated circuit of claim 14, wherein each resistive device comprises an N channel transistor having a drain connected to a corresponding one of the input terminals, a gate connected to a power source terminal to which a power supply voltage is applied, and a source connected to the reference terminal to which the reference potential of a ground level is applied.

Claim 20

The semiconductor integrated circuit of claim 14, wherein each resistive device comprises a P channel transistor having a source connected to a corresponding one of the input terminals, a drain connected to the reference terminal to which the reference potential of a power supply level is applied, and a gate connected to a ground terminal.

Claim 21

The semiconductor integrated circuit of claim 14, wherein each logic circuit comprises at least an inverter connected to a corresponding one of the resistive devices.

Claim 22

The semiconductor integrated circuit of claim 14, wherein the current generating means comprises: a plurality of P channel transistors each having a source, a gate connected to a corresponding one of the logic circuits, and a drain connected to a power supply terminal; and a plurality of transistor groups each having N channel transistors connected in series at drains and sources thereof, a gate and a source of each N channel transistor connected to each other, a drain of one end transistor of series-connected N channel transistors connected to the source of a corresponding one of the P channel transistors and a source of another end transistor of the series-connected N channel transistors connected to an observation terminal.