Quasi-synchronous detection and demodulation circuit and frequency discriminator used for the same

Claim 2

A quasi-synchronous detection and demodulation device, comprising: quadrature detection means for performing a quasi-synchronous detection of a quadrature amplitude modulation signal and for issuing two series of quadrature detection signals; phase rotating means for rotating in phase said quadrature detection signals from said quadrature detection means to issue two series of demodulation signals with no rotation; carrier generating means for providing an output carrier signal having phase rotation information to said phase rotating means; frame-pattern detecting means for detecting a frame-pattern with two series of demodulation signals from said phase rotating means; and carrier phase compensating means for compensating an output carrier phase from said carrier generating means added to said phase rotating means to detect a normal frame pattern by means of said frame pattern detecting means.

Claim 3

A quasi-synchronous detection and demodulation device according to claim 1, wherein said carrier generating means accumulates as an address an error signal based on a phase error from said phase rotation means and transmits data value read from a memory as an output carrier signal; and wherein said carrier phase compensating means adds sequentially an output carrier phase of 0, π/2, π, and 3π/2 to said address value accumulated to fix an added address value of said normal frame pattern detected by said frame pattern detecting means.

Claim 4

A quasi-synchronous detection and demodulation device according to claim 2, wherein said carrier generating means comprises: error signal detecting means for detecting an error signal based on a phase error from said phase rotating means; error signal accumulating means for accumulating said error signal detected by said error signal detecting means to make an address; and a memory for reading data based on said address from said error signal accumulating means to issue it to as an output carrier signal; and said carrier phase compensating means comprises: a judging means for Judging whether said frame-pattern detecting means has detected a normal frame-pattern; a base-4 counter for issuing sequentially an output carrier phase of 0, π/2, π, and 3π/2 and for fixing said output when said judging means judges that said frame-pattern detecting means has detected said normal frame pattern; and adding means for adding an output from said base-4 counter to said address accumulated.

Claim 5

A quasi-synchronous detection and demodulation device according to claim 1, wherein said carrier generating means accumulates as an address an error signal based on a phase signal from said phase rotating means and issues data read from a memory as an output carrier signal; and wherein said carrier phase compensating means continues to add an address to said accumulated error signal, said address to which an output carrier phase is added to π/2, till said frame-pattern detecting means detects a normal frame-pattern.

Claim 6

A quasi-synchronous detection and demodulation device according to claim 4, wherein said carrier generating means comprises: error signal detecting means for detecting an error signal based on a phase error from said phase rotating means; error signal accumulating means for accumulating said error signal detected by said error signal detecting means to make an address; and a memory for reading a data value based on said address from said error signal accumulating means and for issuing it as an output carrier signal; and said carrier phase compensating means comprises: a judging means for judging whether said frame-pattern detecting means has detected a normal frame-pattern; π/2 address generating means for issuing an address value to which an output carrier phase is added by π/2 till said judging means detects a normal frame pattern by means of said frame pattern detecting means; and adding means for adding the output from said π/2 address generating means to said accumulated error signal.

Claim 7

A quasi-synchronous detection and demodulation device according to claim 1, wherein said carrier generating means accumulates as an address an error signal based on a phase error from said phase rotating means and issues a data value read out from a memory as an output carrier signal; and wherein said carrier phase compensating means detects a contingent phase difference from a frame-pattern detected by means of said frame-pattern detecting means and adds an address value corresponding to a detected phase difference to said accumulated address value.

Claim 8

A quasi-synchronous detection and demodulation device according to claim 6, wherein said carrier generating means comprises: error signal detecting means for detecting an error signal based on a phase error from said phase rotating means; error signal accumulating means for accumulating said error signal detected by said error signal detecting means to make an address; and a memory for reading a data value based on said address from said error signal accumulating means and for issuing it as an output carrier signal; and said carrier phase compensating means comprises: a contingent phase difference detecting means for detecting a contingent phase difference according to a frame pattern detected by means of said frame pattern detecting means; address value generating means for generating an address value corresponding to a phase difference detected by means of said contingent phase difference detecting means; and adding means for adding an address value generated from said address generating means to said accumulated address.