End of packet detector and resynchronizer for serial data buses

Claim 2

An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock, including; means, connected to the bus, for receiving bus data and bus clock from a transmission of a packet on the bus; an input buffer, coupled to the means for receiving, having N data locations to store bus data received from the bus in a data location indicated by an input pointer in response to the bus clock; an input pointer generator, coupled to the means for receiving and the input buffer, to supply the input pointer to the input buffer indicating one of the N data locations in a circular sequence for storage of bus data in response to the bus clock beginning in a particular location during a first bus clock in a packet; an output selector, having a selector output and N inputs coupled to the N data locations in the input buffer, to supply bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer; and an output pointer generator, coupled to the means for receiving and the local clock source, to supply an output pointer indicating one of the N data locations in a circular sequence for output of bus data in response to the local clock beginning in the particular location in a local clock cycle after the first bus clock in the packet; and means, coupled to the bus, for detecting an end of a packet of data independent of control data in the packet.

Claim 3

The interface device of claim 1, further including: means, coupled to the means for resynchronizing, for transmitting resynchronized data on the bus or accepting resynchronized data for local processing in response to control data in the packet.

Claim 4

The interface device of claim 2, further including: means, coupled to the means for resynchronizing, for detecting errors in a packet of resynchronized data accepted for local processing in response to control data in the packet.

Claim 5

The interface device of claim 1, wherein the means for detecting an end of a packet includes: means, coupled to the input pointer generator an the output pointer generator, for indicating an end of a packet in response to a match of the input pointer and the output pointer.

Claim 6

An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock, including means, connected to the bus, for receiving bus data and bus clock from a transmission of a packet on the bus; an input buffer, coupled to the means for receiving, having N data locations to store bus data received from the bus in a data location indicated by an input pointer in response to the bus clock; an input pointer generator, coupled to the means for receiving and the input buffer, to supply the input pointer to the input buffer indicating one of the N data locations in a circular sequence for storage of bus data in response to the bus clock beginning in a particular location during a first bus clock in a packet; an output selector, having a selector output and N inputs coupled to the N data locations in the input buffer, to supply bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer; and an output pointer generator, coupled to the means for receiving and the local clock source, to supply an output pointer indicating one of the N data locations in a circular sequence for output of bus data in response to the local clock beginning in the particular location in a local clock cycle after the first bus clock in the packet; means, coupled to the means for resynchronizing, for transmitting resynchronized data on the bus or accepting resynchronized data for local processing in response to control data in the packet; means, coupled to the means for resynchronizing, for detecting an end of a packet of data independent of control data in the packet; and means, coupled to the means for resynchronizing and the means for detecting an end of a packet, for detecting errors in a packet of resynchronized data accepted for local processing in response to control data in the packet.

Claim 7

An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock, including means, connected to the bus, for receiving bus data and bus clock from a transmission of a packet on the bus; an input buffer, coupled to the means for receiving, having N data locations to store bus data received from the bus in a data location indicated by an input pointer in response to the bus clock; an input pointer generator, coupled to the means for receiving and the input buffer, to supply the input pointer to the input buffer indicating one of the N data locations in a circular sequence for storage of bus data in response to the bus clock beginning in a particular location during a first bus clock in a packet; an output selector, having a selector output and N inputs coupled to the N data locations in the input buffer, to supply bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer; and an output pointer generator, coupled to the means for receiving and the local clock source, to supply an output pointer indicating one of the N data locations in a circular sequence for output of bus data in response to the local clock beginning in the particular location in a local clock cycle after the first bus clock in the packet; means, coupled to the means for resynchronizing, for transmitting resynchronized data on the bus or accepting resynchronized data for local processing in response to control data in the packet; means, coupled to the means for resynchronizing, for detecting an end of a packet of data independent of control data in the packet; and means, coupled to the means for resynchronizing and the means for detecting an end of a packet, for detecting errors in a packet of resynchronized data accepted for local processing in response to control data in the packet.

Claim 8

The interface device of claim 5, wherein the means for detecting an end of a packet includes: means, coupled to the input pointer generator and the output pointer generator, for indicating an end of a packet in response to a match of the input pointer and the output pointer.

Claim 9

An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets, comprising: means, connected to the bus, for receiving bus data and bus clock from a transmission of a packet on the bus; an input buffer, coupled to the means for receiving, having N data locations to store bus data received from the bus in a data location indicated by an input pointer in response to the bus clock; an input pointer generator, coupled to the means for receiving and the input buffer, to supply the input pointer to the input buffer indicating one of the N data locations in a circular sequence for storage of bus data in response to the bus clock beginning in a particular location during a first bus clock in a packet; a local clock source supplying a local clock; an output selector, having a selector output and N inputs coupled to the N data locations in the input buffer, to supply bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer; an output pointer generator, coupled to the means for receiving and the local clock source, to supply an output pointer indicating one of the N data locations in a circular sequence for output of bus data in response to the local clock beginning in the particular location in a local clock cycle after the first bus clock in the packet; and comparator means, coupled to the input pointer generator and the output pointer generator, for indicating an end of a packet, and resetting the input pointer and the output pointer to the particular location in response to a match of the input pointer and the output pointer.

Claim 10

An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets, comprising: means, connected to the bus, for receiving bus data and bus clock from a transmission of a packet on the bus; an input buffer, coupled to the means for receiving, having N data locations to store bus data received from the bus in a data location indicated by an input pointer in response to the bus clock; an input pointer generator, coupled to the means for receiving and the input buffer, to supply the input pointer to the input buffer indicating one of the N data locations in a circular sequence for storage of bus data in response to the bus clock beginning in a particular location during a first bus clock in a packet; a local clock source supplying a local clock; an output selector, having a selector output and N inputs coupled to the N data locations in the input buffer, to supply bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer; an output pointer generator, coupled to the means for receiving and the local clock source, to supply an output pointer indicating one of the N data locations in a circular sequence for output of bus data in response to the local clock beginning in the particular location in a local clock cycle after the first bus clock in the packet; and comparator means, coupled to the input pointer generator and the output pointer generator, for indicating an end of a packet, and resetting the input pointer and the output pointer to the particular location in response to a match of the input pointer and the output pointer.

Claim 11

The interface device of claim 7, including: means, coupled to the bus clock and the local clock, for enabling the output pointer generator to increment after the first bus clock in a packet and in synchronization with the local clock.

Claim 12

The interface device of claim 8, wherein the means for enabling includes: first means for asserting a packet start signal in response to the bus clock; a first register, coupled to receive the packet start signal from the first means and to the local clock, for registering the packet start signal on a first local clock after the packet start signal; and a second register, coupled to receive the packet start signal from the first register and to the local clock, for registering the packet start signal on a second local clock after the packet start signal to produce an increment enable signal; and means, coupled with the output pointer generator, for enabling the output pointer generator to increment in response to the increment enable signal.

Claim 13

The device of claim 7, including: means, coupled to the bus clock and the comparator means, for enabling the comparator means on the first bus clock of a packet.

Claim 14

The device of claim 10, wherein the means for enabling is responsive to a packet start signal and includes means for asserting a packet start signal in response to the first bus clock in a packet.

Claim 15

The device of claim 7, wherein the output pointer generator includes a counter clocked by the local clock.

Claim 16

The device of claim 7, wherein the input pointer generator includes a shift register clocked by the bus clock.

Claim 17

The device of claim 7, wherein the input buffer includes N registers having respective clock inputs connected to receive bus clock, data inputs connected to receive bus data, and enable inputs connected to the input pointer.

Claim 18

The device of claim 14, wherein the input pointer generator includes a shift register clocked by the bus clock and having N outputs connected to the enable inputs of respective registers in the input buffer.