Decision-feedback equalizer for cancelling CW interference

Claim 2

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first delay-line taps for producing successively delayed versions of the received signal at said first delay-line taps, first tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a decision error detector for detecting a decision error between the input and output of said decision circuit; a plurality of first tap-gain control circuits for deriving first tap-gain signals from the detected decision error and the delayed signals at said first delay-line taps and respectively applying the first tap-gain signals to said first tap-gain multipliers; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line for defining second delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of second tap-gain control circuits for deriving second tap-gain signals from the detected decision error and the delayed signals at said second delay-line taps and respectively applying the second tap-gain signals to said second tap-gain multipliers, a complex correlator for detecting a correlation between signals at opposite ends of said first tapped delay line; means for comparing the detected correlation with a reference value and causing said first tap-gain control circuits and said second tap-gain control circuits to hold said tap-gain signals at most recently attained amplitude values when the detected correlation is lower than the reference value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 3

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of tap-gain control circuits for detecting correlations between the input signal received by said first tapped delay line and the delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N to produce N tap-gain signals and applying the N tap-gain signals respectively to said first N tap-gain multipliers and said N second tap-gain multipliers; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 4

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of tap-gain control circuits for detecting correlations between the input signal received by said first tapped delay line and the delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N to produce N tap-gain signals and applying the N tap-gain signals respectively to said first N tap-gain multipliers and said N second tap-gain multipliers; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 5

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of first tap-gain control circuits for detecting correlations between the input signal received by said first tapped delay line and the delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N and producing first N tap-gain signals; a decision error detector for detecting a decision error between the input and output of said decision circuit; a plurality of second tap-gain control circuits for deriving second N tap-gain signals from the detected decision error and the delayed signals at said first delay-line taps; a plurality of third tap-gain control circuits for deriving third N tap-gain signals from the detected decision error and the delayed signals at said second delay-line taps; means for detecting a root-mean-square value of the detected decision error, determining whether the root-mean-square value is higher or lower than a prescribed value; switch means for establishing first paths for respectively coupling said first N tap-gain signals to said first N tap-gain multipliers and said second N tap-gain multipliers when the root-mean-square value is determined to be higher than the prescribed value and clearing said first paths and establishing second paths for respectively coupling said second N tap-gain signals to said first N tap-gain multipliers and respectively coupling said third N tap-gain signals to said second N tap-gain multipliers when the root-mean-square value is determined to be lower than the prescribed value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 6

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of first tap-gain control circuits for detecting correlations between the input signal received by said first tapped delay line and the delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N and producing first N tap-gain signals; a decision error detector for detecting a decision error between the input and output of said decision circuit; a plurality of second tap-gain control circuits for deriving second N tap-gain signals from the detected decision error and the delayed signals at said first delay-line taps; a plurality of third tap-gain control circuits for deriving third N tap-gain signals from the detected decision error and the delayed signals at said second delay-line taps; means for detecting a root-mean-square value of the detected decision error, determining whether the root-mean-square value is higher or lower than a prescribed value; switch means for establishing first paths for respectively coupling said first N tap-gain signals to said first N tap-gain multipliers and said second N tap-gain multipliers when the root-mean-square value is determined to be higher than the prescribed value and clearing said first paths and establishing second paths for respectively coupling said second N tap-gain signals to said first N tap-gain multipliers and respectively coupling said third N tap-gain signals to said second N tap-gain multipliers when the root-mean-square value is determined to be lower than the prescribed value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 7

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of tap-gain control circuits for detecting correlations between said input signal received by said first tapped delay line and said delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N to produce N tap-gain signals and applying the N tap-gain signals respectively to said first N tap-gain multipliers and said N second tap-gain multipliers; means for comparing the correlation, which is detected by one of the tap-gain control circuits between signals at opposite ends of the first tapped-delay line, with a reference value and causing said tap-gain control circuits to hold said N tap-gain signals at most recently attained amplitude values when the detected correlation is lower than the reference value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 8

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of tap-gain control circuits for detecting correlations between said input signal received by said first tapped delay line and said delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N to produce N tap-gain signals and applying the N tap-gain signals respectively to said first N tap-gain multipliers and said N second tap-gain multipliers; means for comparing the correlation, which is detected by one of the tap-gain control circuits between signals at opposite ends of the first tapped-delay line, with a reference value and causing said tap-gain control circuits to hold said N tap-gain signals at most recently attained amplitude values when the detected correlation is lower than the reference value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 9

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of first tap-gain control circuits for detecting correlations between the input signal received by said first tapped delay line and the delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N and producing first N tap-gain signals; a decision error detector for detecting a decision error between the input and output of said decision circuit; a plurality of second tap-gain control circuits for deriving second N tap-gain signals from the detected decision error and the delayed signals at said first delay-line taps; a plurality of third tap-gain control circuits for deriving third N tap-gain signals from the detected decision error and the delayed signals at said second delay-line taps; means for detecting a root-mean-square value of the detected decision error, determining whether the root-mean-square value is higher or lower than a prescribed value; switch means for establishing first paths for respectively coupling said first N tap-gain signals to said first N tap-gain multipliers and said N second tap-gain multipliers when the root-mean-square value is determined to be higher than the prescribed value and clearing said first paths and establishing second paths for respectively coupling said second N tap-gain signals to said first N tap-gain multipliers and respectively coupling said third N tap-gain signals to said second N tap-gain multipliers when the root-mean-square value is determined to be lower than the prescribed value; means for determining whether the correlation, which is detected by one of the first tap-gain control circuits between signals at opposite ends of the first tapped-delay line, is higher or lower than a reference value; means for holding ones of said first, second and third N tap-gain signals which are coupled by said switch means to said first and second N tap-gain multipliers at most recently attained amplitude values when the correlation is determined to be lower than the reference value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.

Claim 10

An interference canceller comprising: a feedforward equalizer comprising a first tapped delay line for receiving an input signal and defining first N delay-line taps for producing successively delayed versions of the received input signal at said first delay-line taps, first N tap-gain multipliers for operating on the delayed signals at said first delay-line taps, and first summing means for combining said input signal received by the first tapped delay line and output signals from said first tap-gain multipliers to produce an equalized feedforward output signal; a decision circuit for deriving a decision output signal from an equalized desired signal; a feedback equalizer for operating on the decision output signal from said decision circuit, the feedback equalizer comprising a second tapped delay line defining second N delay-line taps for producing successively delayed versions of said decision output signal at said second delay-line taps, second tap-gain multipliers for operating on the delayed signals at said second delay-line taps, and second summing means for combining output signals from said second tap-gain multipliers to produce an equalized feedback output signal; a plurality of first tap-gain control circuits for detecting correlations between the input signal received by said first tapped delay line and the delayed signals at said first delay-line taps and normalizing each of the detected correlations by a factor which is reciprocal of the integer N and producing first N tap-gain signals; a decision error detector for detecting a decision error between the input and output of said decision circuit; a plurality of second tap-gain control circuits for deriving second N tap-gain signals from the detected decision error and the delayed signals at said first delay-line taps; a plurality of third tap-gain control circuits for deriving third N tap-gain signals from the detected decision error and the delayed signals at said second delay-line taps; means for detecting a root-mean-square value of the detected decision error, determining whether the root-mean-square value is higher or lower than a prescribed value; switch means for establishing first paths for respectively coupling said first N tap-gain signals to said first N tap-gain multipliers and said N second tap-gain multipliers when the root-mean-square value is determined to be higher than the prescribed value and clearing said first paths and establishing second paths for respectively coupling said second N tap-gain signals to said first N tap-gain multipliers and respectively coupling said third N tap-gain signals to said second N tap-gain multipliers when the root-mean-square value is determined to be lower than the prescribed value; means for determining whether the correlation, which is detected by one of the first tap-gain control circuits between signals at opposite ends of the first tapped-delay line, is higher or lower than a reference value; means for holding ones of said first, second and third N tap-gain signals which are coupled by said switch means to said first and second N tap-gain multipliers at most recently attained amplitude values when the correlation is determined to be lower than the reference value; and a combiner for combining said equalized feedforward output signal and said equalized feedback output signal and producing and supplying a combined signal to said decision circuit as said equalized desired signal.